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get_bus_cong using sysconf instead 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2442 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Yinghai Lu 2006-10-04 23:57:49 +00:00
parent d95465d08f
commit 6d74d76de4
47 changed files with 673 additions and 362 deletions
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2
src/mainboard/broadcom/blast/cache_as_ram_auto.c
View File

@ -4,7 +4,7 @@
//#define K8_SCAN_PCI_BUS 1
#define K8_4RANK_DIMM_SUPPORT 1
#define QRANK_DIMM_SUPPORT 1
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1

8
src/mainboard/broadcom/blast/cmos.layout
View File

@ -78,10 +78,10 @@ enumerations
7 9 Fallback_HDD
7 10 Fallback_Floppy
#7 3 ROM
8 0 DDR400
8 1 DDR333
8 2 DDR266
8 3 DDR200
8 0 200Mhz
8 1 166Mhz
8 2 133Mhz
8 3 100Mhz
9 0 off
9 1 87.5%
9 2 75.0%

66
src/mainboard/broadcom/blast/get_bus_conf.c
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@ -7,32 +7,8 @@
#include <cpu/amd/dualcore.h>
#endif
unsigned sblk;
unsigned pci1234[] =
{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not
//You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
0x0000ff0,
// 0x0000ff0,
// 0x0000ff0,
// 0x0000ff0,
// 0x0000ff0,
// 0x0000ff0,
// 0x0000ff0,
// 0x0000ff0
};
unsigned hc_possible_num;
unsigned sbdn;
unsigned hcdn[] =
{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
0x20202020,
// 0x20202020,
// 0x20202020,
// 0x20202020,
// 0x20202020,
// 0x20202020,
// 0x20202020,
// 0x20202020,
};
#include <cpu/amd/amdk8_sysconf.h>
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
//busnum is default
@ -43,6 +19,30 @@ unsigned char bus_bcm5785_1 = 8;
unsigned char bus_bcm5785_1_1 = 9;
unsigned apicid_bcm5785[3];
unsigned pci1234x[] =
{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not
//You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
0x0000ff0,
// 0x0000ff0,
// 0x0000ff0,
// 0x0000ff0,
// 0x0000ff0,
// 0x0000ff0,
// 0x0000ff0,
// 0x0000ff0
};
unsigned hcdnx[] =
{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
0x20202020,
// 0x20202020,
// 0x20202020,
// 0x20202020,
// 0x20202020,
// 0x20202020,
// 0x20202020,
// 0x20202020,
};
unsigned sbdn2;
extern void get_sblk_pci1234(void);
@ -61,18 +61,22 @@ void get_bus_conf(void)
get_bus_conf_done = 1;
hc_possible_num = sizeof(pci1234)/sizeof(pci1234[0]);
sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
for(i=0;i<sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i];
}
get_sblk_pci1234();
sbdn = (hcdn[0] >> 8) & 0xff;
sbdn2 = hcdn[0] & 0xff; // bcm5780
sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff;
sbdn2 = sysconf.hcdn[0] & 0xff; // bcm5780
bus_bcm5785_0 = (pci1234[0] >> 16) & 0xff;
bus_bcm5785_0 = (sysconf.pci1234[0] >> 16) & 0xff;
bus_bcm5780[0] = bus_bcm5785_0;
/* bcm5785 */
dev = dev_find_slot(bus_bcm5785_0, PCI_DEVFN(sbdn,0));
dev = dev_find_slot(bus_bcm5785_0, PCI_DEVFN(sysconf.sbdn,0));
if (dev) {
bus_bcm5785_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
dev = dev_find_slot(bus_bcm5785_1, PCI_DEVFN(0x0d,0));

8
src/mainboard/broadcom/blast/irq_tables.c
View File

@ -10,9 +10,7 @@
#include <stdint.h>
#include <arch/pirq_routing.h>
extern unsigned pci1234[];
extern unsigned sbdn;
extern unsigned hcdn[];
#include <cpu/amd/amdk8_sysconf.h>
static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
@ -71,7 +69,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq->version = PIRQ_VERSION;
pirq->rtr_bus = bus_bcm5785_0;
pirq->rtr_devfn = (sbdn<<3)|0;
pirq->rtr_devfn = (sysconf.sbdn<<3)|0;
pirq->exclusive_irqs = 0;
@ -87,7 +85,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq_info = (void *) ( &pirq->checksum + 1);
slot_num = 0;
//pci bridge
write_pirq_info(pirq_info, bus_bcm5785_0, (sbdn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
write_pirq_info(pirq_info, bus_bcm5785_0, (sysconf.sbdn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++;
pirq->size = 32 + 16 * slot_num;

8
src/mainboard/broadcom/blast/mptable.c
View File

@ -8,9 +8,7 @@
#include <cpu/amd/dualcore.h>
#endif
extern unsigned pci1234[];
extern unsigned sbdn;
extern unsigned hcdn[];
#include <cpu/amd/amdk8_sysconf.h>
extern unsigned char bus_isa;
extern unsigned char bus_bcm5780[7];
@ -95,7 +93,7 @@ void *smp_write_config_table(void *v)
//IDE
outb(0x02, 0xc00); outb(0x0e, 0xc01);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_bcm5785_0, ((1+sbdn)<<2)|1, apicid_bcm5785[0], 0xe); // IDE
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, apicid_bcm5785[0], 0xe); // IDE
//SATA
outb(0x07, 0xc00); outb(0x0f, 0xc01);
@ -104,7 +102,7 @@ void *smp_write_config_table(void *v)
//USB
outb(0x01, 0xc00); outb(0x0a, 0xc01);
for(i=0;i<3;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, ((2+sbdn)<<2)|i, apicid_bcm5785[0], 0xa); //
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, apicid_bcm5785[0], 0xa); //
}

17
src/mainboard/tyan/s2881/Options.lb
View File

@ -54,6 +54,11 @@ uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
uses HT_CHAIN_UNITID_BASE
uses HT_CHAIN_END_UNITID_BASE
uses SB_HT_CHAIN_ON_BUS0
uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
@ -121,6 +126,18 @@ default CONFIG_LOGICAL_CPUS=1
#CHIP_NAME ?
default CONFIG_CHIP_NAME=1
##HT Unit ID offset, default is 1, the typical one
default HT_CHAIN_UNITID_BASE=0x0a
##real SB Unit ID, default is 0x20, mean dont touch it at last
default HT_CHAIN_END_UNITID_BASE=0x06
#make the SB HT chain on bus 0, default is not (0)
default SB_HT_CHAIN_ON_BUS0=0
##only offset for SB chain?, default is yes(1)
#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
#1G memory hole
default HW_MEM_HOLE_SIZEK=0x100000

2
src/mainboard/tyan/s2881/auto.c
View File

@ -20,7 +20,7 @@
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/cpu_rev.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"

32
src/mainboard/tyan/s2881/cache_as_ram_auto.c
View File

@ -1,7 +1,7 @@
#define ASSEMBLY 1
#define __ROMCC__
#define K8_4RANK_DIMM_SUPPORT 1
#define QRANK_DIMM_SUPPORT 1
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
@ -19,7 +19,19 @@
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#if 0
static void post_code(uint8_t value) {
#if 1
int i;
for(i=0;i<0x80000;i++) {
outb(value, 0x80);
}
#endif
}
#endif
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
@ -113,9 +125,11 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
enumerate_ht_chain();
/* Setup the ck804 */
amd8111_enable_rom();
/* Is this a deliberate reset by the bios */
// post_code(0x22);
if (bios_reset_detected() && last_boot_normal_x) {
goto normal_image;
}
@ -127,12 +141,14 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
goto fallback_image;
}
normal_image:
// post_code(0x23);
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
);
fallback_image:
// post_code(0x25);
;
}
#endif
@ -170,6 +186,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
bsp_apicid = init_cpus(cpu_init_detectedx);
}
// post_code(0x32);
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
@ -179,6 +196,10 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
report_bist_failure(bist);
setup_s2881_resource_map();
#if 0
dump_pci_device(PCI_DEV(0, 0x18, 0));
dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif
needs_reset = setup_coherent_ht_domain();
@ -197,6 +218,12 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
}
enable_smbus();
#if 0
dump_spd_registers(&cpu[0]);
#endif
#if 0
dump_smbus_registers();
#endif
allow_all_aps_stop(bsp_apicid);
@ -207,6 +234,9 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
memreset_setup();
sdram_initialize(nodes, ctrl);
#if 0
dump_pci_devices();
#endif
post_cache_as_ram();
}

8
src/mainboard/tyan/s2881/cmos.layout
View File

@ -78,10 +78,10 @@ enumerations
7 9 Fallback_HDD
7 10 Fallback_Floppy
#7 3 ROM
8 0 DDR400
8 1 DDR333
8 2 DDR266
8 3 DDR200
8 0 200Mhz
8 1 166Mhz
8 2 133Mhz
8 3 100Mhz
9 0 off
9 1 87.5%
9 2 75.0%

40
src/mainboard/tyan/s2881/get_bus_conf.c
View File

@ -7,6 +7,8 @@
#include <cpu/amd/dualcore.h>
#endif
#include <cpu/amd/amdk8_sysconf.h>
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
//busnum is default
@ -20,8 +22,7 @@ unsigned apicid_8111 ;
unsigned apicid_8131_1;
unsigned apicid_8131_2;
unsigned sblk;
unsigned pci1234[] =
unsigned pci1234x[] =
{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not
//You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
0x0000ff0,
@ -33,9 +34,7 @@ unsigned pci1234[] =
// 0x0000ff0,
// 0x0000ff0
};
unsigned hc_possible_num;
unsigned sbdn;
unsigned hcdn[] =
unsigned hcdnx[] =
{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
0x20202020,
// 0x20202020,
@ -58,23 +57,28 @@ void get_bus_conf(void)
unsigned apicid_base;
device_t dev;
int i;
if(get_bus_conf_done==1) return; //do it only once
if(get_bus_conf_done==1) return; //do it only once
get_bus_conf_done = 1;
get_bus_conf_done = 1;
hc_possible_num = sizeof(pci1234)/sizeof(pci1234[0]);
sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
for(i=0;i<sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i];
}
get_sblk_pci1234();
get_sblk_pci1234();
sbdn = (hcdn[0] >> 8) & 0xff;
sbdn3 = hcdn[0] & 0xff;
sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff;
sbdn3 = sysconf.hcdn[0] & 0xff;
bus_8131_0 = (pci1234[0] >> 16) & 0xff;
bus_8131_0 = (sysconf.pci1234[0] >> 16) & 0xff;
bus_8111_0 = bus_8131_0;
/* 8111 */
dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sbdn,0));
dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sysconf.sbdn,0));
if (dev) {
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
#if HT_CHAIN_END_UNITID_BASE >= HT_CHAIN_UNITID_BASE
@ -91,11 +95,6 @@ void get_bus_conf(void)
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0));
if (dev) {
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
// printk_debug("bus_isa=%d\n",bus_isa);
#endif
}
else {
printk_debug("ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0);
@ -105,6 +104,11 @@ void get_bus_conf(void)
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,0));
if (dev) {
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
// printk_debug("bus_isa=%d\n",bus_isa);
#endif
}
else {
printk_debug("ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);

8
src/mainboard/tyan/s2881/irq_tables.c
View File

@ -10,6 +10,8 @@
#include <stdint.h>
#include <arch/pirq_routing.h>
#include <cpu/amd/amdk8_sysconf.h>
static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
uint8_t slot, uint8_t rfu)
@ -34,8 +36,6 @@ extern unsigned char bus_8131_2;
extern unsigned char bus_8111_0;
extern unsigned char bus_8111_1;
extern unsigned sbdn;
extern unsigned hcdn[];
extern unsigned sbdn3;
extern void get_bus_conf(void);
@ -67,7 +67,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq->version = PIRQ_VERSION;
pirq->rtr_bus = bus_8111_0;
pirq->rtr_devfn = ((sbdn+1)<<3)|0;
pirq->rtr_devfn = ((sysconf.sbdn+1)<<3)|0;
pirq->exclusive_irqs = 0;
@ -81,7 +81,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq_info = (void *) ( &pirq->checksum + 1);
slot_num = 0;
//pci bridge
write_pirq_info(pirq_info, bus_8111_0, ((sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
write_pirq_info(pirq_info, bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++;
//pcix bridge
// write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);

8
src/mainboard/tyan/s2881/mptable.c
View File

@ -4,6 +4,8 @@
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdk8_sysconf.h>
extern unsigned char bus_isa;
extern unsigned char bus_8131_0;
extern unsigned char bus_8131_1;
@ -14,14 +16,10 @@ extern unsigned apicid_8111;
extern unsigned apicid_8131_1;
extern unsigned apicid_8131_2;
extern unsigned sbdn;
extern unsigned hcdn[];
extern unsigned sbdn3;
extern void get_bus_conf(void);
void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
@ -100,7 +98,7 @@ void *smp_write_config_table(void *v)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_8111, 0xf);
//8111 LPC ????
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sbdn+1)<<2)|0, apicid_8111, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|0, apicid_8111, 0x13);
//On Board AMD USB ???
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13);

19
src/mainboard/tyan/s2885/Options.lb
View File

@ -63,6 +63,13 @@ uses ENABLE_APIC_EXT_ID
uses APIC_ID_OFFSET
uses LIFT_BSP_APIC_ID
uses HT_CHAIN_UNITID_BASE
uses HT_CHAIN_END_UNITID_BASE
uses SB_HT_CHAIN_ON_BUS0
uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
uses CONFIG_LB_MEM_TOPK
###
### Build options
###
@ -125,6 +132,18 @@ default CONFIG_LOGICAL_CPUS=1
#CHIP_NAME ?
default CONFIG_CHIP_NAME=1
##HT Unit ID offset, default is 1, the typical one
default HT_CHAIN_UNITID_BASE=0x0a
##real SB Unit ID, default is 0x20, mean dont touch it at last
default HT_CHAIN_END_UNITID_BASE=0x06
#make the SB HT chain on bus 0, default is not (0)
default SB_HT_CHAIN_ON_BUS0=2
##only offset for SB chain?, default is yes(1)
#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
#1G memory hole
default HW_MEM_HOLE_SIZEK=0x100000

2
src/mainboard/tyan/s2885/auto.c
View File

@ -19,7 +19,7 @@
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/cpu_rev.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"

29
src/mainboard/tyan/s2885/cache_as_ram_auto.c
View File

@ -13,7 +13,19 @@
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#if 0
static void post_code(uint8_t value) {
#if 1
int i;
for(i=0;i<0x80000;i++) {
outb(value, 0x80);
}
#endif
}
#endif
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
@ -68,7 +80,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
#define K8_4RANK_DIMM_SUPPORT 1
#define QRANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
@ -113,9 +125,11 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
enumerate_ht_chain();
/* Setup the ck804 */
amd8111_enable_rom();
/* Is this a deliberate reset by the bios */
// post_code(0x22);
if (bios_reset_detected() && last_boot_normal_x) {
goto normal_image;
}
@ -127,12 +141,14 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
goto fallback_image;
}
normal_image:
// post_code(0x23);
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
);
fallback_image:
// post_code(0x25);
;
}
#endif
@ -170,15 +186,22 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
bsp_apicid = init_cpus(cpu_init_detectedx);
}
// post_code(0x32);
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE);
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
setup_s2885_resource_map();
#if 0
dump_pci_device(PCI_DEV(0, 0x18, 0));
dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif
needs_reset = setup_coherent_ht_domain();
@ -208,6 +231,10 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
memreset_setup();
sdram_initialize(nodes, ctrl);
#if 0
dump_pci_devices();
#endif
post_cache_as_ram();
}

8
src/mainboard/tyan/s2885/cmos.layout
View File

@ -78,10 +78,10 @@ enumerations
7 9 Fallback_HDD
7 10 Fallback_Floppy
#7 3 ROM
8 0 DDR400
8 1 DDR333
8 2 DDR266
8 3 DDR200
8 0 200Mhz
8 1 166Mhz
8 2 133Mhz
8 3 100Mhz
9 0 off
9 1 87.5%
9 2 75.0%

44
src/mainboard/tyan/s2885/get_bus_conf.c
View File

@ -7,6 +7,7 @@
#include <cpu/amd/dualcore.h>
#endif
#include <cpu/amd/amdk8_sysconf.h>
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
//busnum is default
@ -22,8 +23,7 @@ unsigned apicid_8111 ;
unsigned apicid_8131_1;
unsigned apicid_8131_2;
unsigned sblk;
unsigned pci1234[] =
unsigned pci1234x[] =
{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not
//You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
0x0000ff0,
@ -35,9 +35,7 @@ unsigned pci1234[] =
// 0x0000ff0,
// 0x0000ff0
};
unsigned hc_possible_num;
unsigned sbdn;
unsigned hcdn[] =
unsigned hcdnx[] =
{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
0x20202020,
0x20202020,
@ -61,24 +59,29 @@ void get_bus_conf(void)
unsigned apicid_base;
device_t dev;
int i;
if(get_bus_conf_done==1) return; //do it only once
if(get_bus_conf_done==1) return; //do it only once
get_bus_conf_done = 1;
get_bus_conf_done = 1;
hc_possible_num = sizeof(pci1234)/sizeof(pci1234[0]);
sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
for(i=0;i<sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i];
}
get_sblk_pci1234();
get_sblk_pci1234();
sbdn = (hcdn[0] >> 8) & 0xff;
sbdn3 = hcdn[0] & 0xff;
sbdn5 = hcdn[1] & 0xff;
sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff;
sbdn3 = sysconf.hcdn[0] & 0xff;
sbdn5 = sysconf.hcdn[1] & 0xff;
bus_8131_0 = (pci1234[0] >> 16) & 0xff;
bus_8131_0 = (sysconf.pci1234[0] >> 16) & 0xff;
bus_8111_0 = bus_8131_0;
/* 8111 */
dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sbdn,0));
dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sysconf.sbdn,0));
if (dev) {
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
#if HT_CHAIN_END_UNITID_BASE >= HT_CHAIN_UNITID_BASE
@ -95,11 +98,6 @@ void get_bus_conf(void)
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0));
if (dev) {
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
// printk_debug("bus_isa=%d\n",bus_isa);
#endif
}
else {
printk_debug("ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0);
@ -109,6 +107,12 @@ void get_bus_conf(void)
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,0));
if (dev) {
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
// printk_debug("bus_isa=%d\n",bus_isa);
#endif
}
else {
printk_debug("ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
@ -116,7 +120,7 @@ void get_bus_conf(void)
/* HT chain 1 */
// it is on node0, so it must be there
bus_8151_0 = (pci1234[1] >> 16) & 0xff;
bus_8151_0 = (sysconf.pci1234[1] >> 16) & 0xff;
/* 8151 */
dev = dev_find_slot(bus_8151_0, PCI_DEVFN(sbdn5+1, 0));

8
src/mainboard/tyan/s2885/irq_tables.c
View File

@ -10,6 +10,8 @@
#include <stdint.h>
#include <arch/pirq_routing.h>
#include <cpu/amd/amdk8_sysconf.h>
static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
uint8_t slot, uint8_t rfu)
@ -36,8 +38,6 @@ extern unsigned char bus_8111_1;
extern unsigned char bus_8151_0;
extern unsigned char bus_8151_1;
extern unsigned sbdn;
extern unsigned hcdn[];
extern unsigned sbdn3;
extern unsigned sbdn5;
@ -70,7 +70,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq->version = PIRQ_VERSION;
pirq->rtr_bus = bus_8111_0;
pirq->rtr_devfn = ((sbdn+1)<<3)|0;
pirq->rtr_devfn = ((sysconf.sbdn+1)<<3)|0;
pirq->exclusive_irqs = 0;
@ -84,7 +84,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq_info = (void *) ( &pirq->checksum + 1);
slot_num = 0;
//pci bridge
write_pirq_info(pirq_info, bus_8111_0, ((sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
write_pirq_info(pirq_info, bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++;
//pcix bridge
// write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);

8
src/mainboard/tyan/s2885/mptable.c
View File

@ -4,6 +4,8 @@
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdk8_sysconf.h>
extern unsigned char bus_isa;
extern unsigned char bus_8131_0;
extern unsigned char bus_8131_1;
@ -16,8 +18,6 @@ extern unsigned apicid_8111;
extern unsigned apicid_8131_1;
extern unsigned apicid_8131_2;
extern unsigned sbdn;
extern unsigned hcdn[];
extern unsigned sbdn3;
extern unsigned sbdn5;
@ -99,9 +99,9 @@ void *smp_write_config_table(void *v)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_8111, 0xe);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_8111, 0xf);
//??? What
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sbdn+1)<<2)|3, apicid_8111, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|3, apicid_8111, 0x13);
//Onboard AMD AC97 Audio
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sbdn+1)<<2)|1, apicid_8111, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|1, apicid_8111, 0x11);
// Onboard AMD USB
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13);

4
src/mainboard/tyan/s2891/Config.lb
View File

@ -314,8 +314,8 @@ chip northbridge/amd/amdk8/root_complex
# chip drivers/ati/ragexl
chip drivers/pci/onboard
device pci 7.0 on end
# register "rom_address" = "0xfff80000" #for 512K
register "rom_address" = "0xfff00000" #for 1M
register "rom_address" = "0xfff80000" #for 512K
# register "rom_address" = "0xfff00000" #for 1M
end
end
device pci a.0 off end # NIC

16
src/mainboard/tyan/s2891/Options.lb
View File

@ -54,7 +54,6 @@ uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
uses K8_HT_FREQ_1G_SUPPORT
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
@ -74,12 +73,13 @@ uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
uses CONFIG_LB_MEM_TOPK
## ROM_SIZE is the size of boot ROM that this board will use.
#512K bytes
#default ROM_SIZE=524288
default ROM_SIZE=524288
#1M bytes
default ROM_SIZE=1048576
#default ROM_SIZE=1048576
##
@ -139,9 +139,6 @@ default CONFIG_LOGICAL_CPUS=1
#1G memory hole
default HW_MEM_HOLE_SIZEK=0x100000
#Opteron K8 1G HT Support
default K8_HT_FREQ_1G_SUPPORT=1
##HT Unit ID offset, default is 1, the typical one
default HT_CHAIN_UNITID_BASE=0x0
@ -152,8 +149,7 @@ default HT_CHAIN_UNITID_BASE=0x0
default SB_HT_CHAIN_ON_BUS0=2
##only offset for SB chain?, default is yes(1)
default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
#BTEXT Console
#default CONFIG_CONSOLE_BTEXT=1
@ -229,8 +225,8 @@ default CONFIG_ROM_STREAM = 1
##
## The default compiler
##
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
default CC="$(CROSS_COMPILE)gcc-3.3.6 -m32"
default HOSTCC="gcc-3.3.6"
##
## Disable the gdb stub by default

2
src/mainboard/tyan/s2891/auto.c
View File

@ -12,7 +12,7 @@
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/cpu_rev.c"
#define K8_HT_FREQ_1G_SUPPORT 0
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/nvidia/ck804/ck804_early_smbus.c"

48
src/mainboard/tyan/s2891/cache_as_ram_auto.c
View File

@ -2,7 +2,7 @@
#define __ROMCC__
//used by raminit
#define K8_4RANK_DIMM_SUPPORT 1
#define QRANK_DIMM_SUPPORT 1
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
@ -21,7 +21,19 @@
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#if 0
static void post_code(uint8_t value) {
#if 1
int i;
for(i=0;i<0x80000;i++) {
outb(value, 0x80);
}
#endif
}
#endif
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/nvidia/ck804/ck804_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
@ -42,6 +54,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
static void memreset_setup(void)
{
}
@ -92,15 +105,21 @@ static void sio_setup(void)
uint32_t dword;
uint8_t byte;
byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
/* subject decoding*/
byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
byte |= 0x20;
pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
/* LPC Positive Decode 0 */
dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
/* Serial 0, Serial 1 */
dword |= (1<<0) | (1<<1);
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
#if 1
/* s2891 has onboard LPC port 80 */
/*Hope I can enable port 80 here
It will decode port 80 to LPC, If you are using PCI post code you can not do this */
dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4);
dword |= (1<<16);
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
@ -133,6 +152,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
ck804_enable_rom();
/* Is this a deliberate reset by the bios */
// post_code(0x22);
if (bios_reset_detected() && last_boot_normal_x) {
goto normal_image;
}
@ -144,12 +164,14 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
goto fallback_image;
}
normal_image:
// post_code(0x23);
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) , "b" (cpu_init_detectedx)/* inputs */
);
fallback_image:
// post_code(0x25);
;
}
#endif
@ -187,6 +209,8 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
bsp_apicid = init_cpus(cpu_init_detectedx);
}
// post_code(0x32);
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
@ -195,6 +219,10 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
report_bist_failure(bist);
setup_s2891_resource_map();
#if 0
dump_pci_device(PCI_DEV(0, 0x18, 0));
dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif
needs_reset = setup_coherent_ht_domain();
@ -211,7 +239,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (needs_reset) {
print_info("ht reset -\r\n");
soft_reset();
// soft_reset();
}
allow_all_aps_stop(bsp_apicid);
@ -221,9 +249,23 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
fill_mem_ctrl(nodes, ctrl, spd_addr);
enable_smbus();
#if 0
dump_spd_registers(&cpu[0]);
#endif
#if 0
dump_smbus_registers();
#endif
memreset_setup();
sdram_initialize(nodes, ctrl);
#if 0
print_pci_devices();
#endif
#if 0
dump_pci_devices();
#endif
post_cache_as_ram();
}

8
src/mainboard/tyan/s2891/cmos.layout
View File

@ -78,10 +78,10 @@ enumerations
7 9 Fallback_HDD
7 10 Fallback_Floppy
#7 3 ROM
8 0 DDR400
8 1 DDR333
8 2 DDR266
8 3 DDR200
8 0 200Mhz
8 1 166Mhz
8 2 133Mhz
8 3 100Mhz
9 0 off
9 1 87.5%
9 2 75.0%

53
src/mainboard/tyan/s2891/get_bus_conf.c
View File

@ -7,6 +7,7 @@
#include <cpu/amd/dualcore.h>
#endif
#include <cpu/amd/amdk8_sysconf.h>
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
//busnum is default
@ -25,8 +26,8 @@
unsigned apicid_8131_1;
unsigned apicid_8131_2;
unsigned sblk;
unsigned pci1234[] =
unsigned pci1234x[] =
{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not
//You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
0x0000000,
@ -38,9 +39,7 @@ unsigned pci1234[] =
// 0x0000ff0,
// 0x0000ff0
};
unsigned hc_possible_num;
unsigned sbdn;
unsigned hcdn[] =
unsigned hcdnx[] =
{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
0x20202020,
0x20202020,
@ -65,27 +64,27 @@ void get_bus_conf(void)
unsigned apicid_base;
device_t dev;
unsigned sbdn;
int i;
if(get_bus_conf_done==1) return; //do it only once
if(get_bus_conf_done==1) return; //do it only once
get_bus_conf_done = 1;
get_bus_conf_done = 1;
hc_possible_num = sizeof(pci1234)/sizeof(pci1234[0]);
get_sblk_pci1234();
sbdn = (hcdn[0] & 0xff); // first byte of first chain
sbdn3 = (hcdn[1] & 0xff); // first byte of second chain
// bus_ck804_0 = node_link_to_bus(0, sblk);
bus_ck804_0 = (pci1234[0] >> 16) & 0xff;
if(pci1234[2] & 1) {
bus_coproc_0 = (pci1234[2] >> 16) & 0xff;
coprocdn = (hcdn[2] & 0xff);
sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
for(i=0;i<sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i];
}
get_sblk_pci1234();
sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
sbdn = sysconf.sbdn;
sbdn3 = (sysconf.hcdn[1] & 0xff); // first byte of second chain
bus_ck804_0 = (sysconf.pci1234[0] >> 16) & 0xff;
/* CK804 */
@ -153,16 +152,14 @@ void get_bus_conf(void)
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x0e,0));
if (dev) {
bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_8131_0 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_8131_0++;
bus_isa = bus_8131_0; // incase only one installed
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
}
else {
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn+ 0x0e);
}
bus_8131_0 = (pci1234[1] >> 16) & 0xff;
bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff;
/* 8131-1 */
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0));
@ -191,6 +188,10 @@ void get_bus_conf(void)
bus_isa = bus_8131_1+2;
}
if(sysconf.pci1234[2] & 1) {
bus_coproc_0 = (sysconf.pci1234[2] >> 16) & 0xff;
coprocdn = (sysconf.hcdn[2] & 0xff);
}
/*I/O APICs: APIC ID Version State Address*/

18
src/mainboard/tyan/s2891/irq_tables.c
View File

@ -10,6 +10,8 @@
#include <stdint.h>
#include <arch/pirq_routing.h>
#include <cpu/amd/amdk8_sysconf.h>
static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
uint8_t slot, uint8_t rfu)
@ -40,10 +42,7 @@ extern unsigned char bus_8131_1;//8
extern unsigned char bus_8131_2;//9
extern unsigned char bus_coproc_0;
extern unsigned sbdn;
extern unsigned hcdn[];
extern unsigned sbdn3;
extern unsigned pci1234[];
extern unsigned coprocdn;
extern void get_bus_conf(void);
@ -58,8 +57,10 @@ unsigned long write_pirq_routing_table(unsigned long addr)
uint8_t sum=0;
int i;
unsigned sbdn;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
sbdn = sysconf.sbdn;
/* Align the table to be 16 byte aligned. */
addr += 15;
@ -94,12 +95,11 @@ unsigned long write_pirq_routing_table(unsigned long addr)
//pcix bridge
write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++;
//co processor
if(pci1234[2] & 1) {
write_pirq_info(pirq_info, bus_coproc_0, (coprocdn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++;
}
if(sysconf.pci1234[2] & 1) {
write_pirq_info(pirq_info, bus_coproc_0, (coprocdn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++;
}
#if 0
//smbus

8
src/mainboard/tyan/s2891/mptable.c
View File

@ -4,6 +4,8 @@
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdk8_sysconf.h>
extern unsigned char bus_isa;
extern unsigned char bus_ck804_0; //1
extern unsigned char bus_ck804_1; //2
@ -18,8 +20,6 @@ extern unsigned apicid_ck804;
extern unsigned apicid_8131_1;
extern unsigned apicid_8131_2;
extern unsigned sbdn;
extern unsigned hcdn[];
extern unsigned sbdn3;
extern void get_bus_conf(void);
@ -30,6 +30,7 @@ void *smp_write_config_table(void *v)
static const char oem[8] = "TYAN ";
static const char productid[12] = "S2891 ";
struct mp_config_table *mc;
unsigned sbdn;
unsigned char bus_num;
int i;
@ -54,6 +55,7 @@ void *smp_write_config_table(void *v)
smp_write_processors(mc);
get_bus_conf();
sbdn = sysconf.sbdn;
/*Bus: Bus ID Type*/
/* define bus and isa numbers */
@ -75,6 +77,7 @@ void *smp_write_config_table(void *v)
smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
}
/* Initialize interrupt mapping*/
dword = 0x0000d218;
pci_write_config32(dev, 0x7c, dword);
@ -83,7 +86,6 @@ void *smp_write_config_table(void *v)
pci_write_config32(dev, 0x80, dword);
dword = 0x0000007d;
pci_write_config32(dev, 0x84, dword);
}

4
src/mainboard/tyan/s2891/resourcemap.c
View File

@ -258,8 +258,8 @@ static void setup_s2891_resource_map(void)
* This field defines the highest bus number in configuration region i
*/
#if 1
// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003,
// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203,
// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, /* link 0 of cpu 0 --> Nvidia CK 804 Pro */
// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 */
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
#endif

3
src/mainboard/tyan/s2892/Config.lb
View File

@ -313,8 +313,7 @@ chip northbridge/amd/amdk8/root_complex
# chip drivers/ati/ragexl
chip drivers/pci/onboard
device pci 6.0 on end
# register "rom_address" = "0xfff80000" #for 512K
register "rom_address" = "0xfff00000" #for 1M
register "rom_address" = "0xfff80000"
end
chip drivers/pci/onboard
device pci 8.0 on end

17
src/mainboard/tyan/s2892/Options.lb
View File

@ -54,7 +54,6 @@ uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
uses K8_HT_FREQ_1G_SUPPORT
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
@ -66,12 +65,14 @@ uses HT_CHAIN_END_UNITID_BASE
uses SB_HT_CHAIN_ON_BUS0
uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
uses CONFIG_LB_MEM_TOPK
## ROM_SIZE is the size of boot ROM that this board will use.
#512K bytes
#default ROM_SIZE=524288
default ROM_SIZE=524288
#1M bytes
default ROM_SIZE=1048576
#default ROM_SIZE=1048576
##
@ -128,12 +129,6 @@ default CONFIG_MAX_CPUS=4
default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=1
#1G memory hole
default HW_MEM_HOLE_SIZEK=0x100000
#Opteron K8 1G HT Support
default K8_HT_FREQ_1G_SUPPORT=1
##HT Unit ID offset, default is 1, the typical one
default HT_CHAIN_UNITID_BASE=0x0
@ -146,6 +141,9 @@ default SB_HT_CHAIN_ON_BUS0=2
##only offset for SB chain?, default is yes(1)
default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
#1G memory hole
default HW_MEM_HOLE_SIZEK=0x100000
#BTEXT Console
#default CONFIG_CONSOLE_BTEXT=1
@ -161,6 +159,7 @@ default DCACHE_RAM_BASE=0xcf000
default DCACHE_RAM_SIZE=0x1000
default CONFIG_USE_INIT=0
##
## Build code to setup a generic IOAPIC
##

2
src/mainboard/tyan/s2892/auto.c
View File

@ -12,7 +12,7 @@
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/cpu_rev.c"
#define K8_HT_FREQ_1G_SUPPORT 1
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/nvidia/ck804/ck804_early_smbus.c"

105
src/mainboard/tyan/s2892/cache_as_ram_auto.c
View File

@ -13,6 +13,17 @@
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#if 0
static void post_code(uint8_t value) {
#if 1
int i;
for(i=0;i<0x80000;i++) {
outb(value, 0x80);
}
#endif
}
#endif
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/nvidia/ck804/ck804_early_smbus.c"
@ -54,7 +65,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
#define K8_4RANK_DIMM_SUPPORT 1
#define QRANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
@ -98,7 +109,7 @@ static void sio_setup(void)
uint32_t dword;
uint8_t byte;
byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
byte |= 0x20;
pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
@ -106,7 +117,6 @@ static void sio_setup(void)
dword |= (1<<0);
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
}
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{
@ -132,6 +142,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
ck804_enable_rom();
/* Is this a deliberate reset by the bios */
// post_code(0x22);
if (bios_reset_detected() && last_boot_normal_x) {
goto normal_image;
}
@ -143,12 +154,14 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
goto fallback_image;
}
normal_image:
// post_code(0x23);
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist), "b"(cpu_init_detectedx) /* inputs */
);
fallback_image:
// post_code(0x25);
;
}
#endif
@ -167,46 +180,42 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const struct mem_controller cpu[] = {
{
.node_id = 0,
.f0 = PCI_DEV(0, 0x18, 0),
.f1 = PCI_DEV(0, 0x18, 1),
.f2 = PCI_DEV(0, 0x18, 2),
.f3 = PCI_DEV(0, 0x18, 3),
.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
},
#if CONFIG_MAX_PHYSICAL_CPUS > 1
{
.node_id = 1,
.f0 = PCI_DEV(0, 0x19, 0),
.f1 = PCI_DEV(0, 0x19, 1),
.f2 = PCI_DEV(0, 0x19, 2),
.f3 = PCI_DEV(0, 0x19, 3),
.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
},
#endif
};
unsigned bsp_apicid = 0;
static const uint16_t spd_addr [] = {
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
(0xa<<3)|1, (0xa<<3)|3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
(0xa<<3)|4, (0xa<<3)|6, 0, 0,
(0xa<<3)|5, (0xa<<3)|7, 0, 0,
#endif
};
int needs_reset;
unsigned bsp_apicid = 0;
struct mem_controller ctrl[8];
unsigned nodes;
if (bist == 0) {
init_cpus(cpu_init_detectedx);
}
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
// post_code(0x32);
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
setup_s2892_resource_map();
#if 0
dump_pci_device(PCI_DEV(0, 0x18, 0));
dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif
needs_reset = setup_coherent_ht_domain();
needs_reset = setup_coherent_ht_domain();
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS==1
@ -219,15 +228,35 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ck804_early_setup_x();
if (needs_reset) {
print_info("ht reset -\r\n");
soft_reset();
}
if (needs_reset) {
print_info("ht reset -\r\n");
soft_reset();
}
enable_smbus();
allow_all_aps_stop(bsp_apicid);
memreset_setup();
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
nodes = get_nodes();
//It's the time to set ctrl now;
fill_mem_ctrl(nodes, ctrl, spd_addr);
post_cache_as_ram();
enable_smbus();
#if 0
dump_spd_registers(&cpu[0]);
#endif
#if 0
dump_smbus_registers();
#endif
memreset_setup();
sdram_initialize(nodes, ctrl);
#if 0
print_pci_devices();
#endif
#if 0
dump_pci_devices();
#endif
post_cache_as_ram();
}

8
src/mainboard/tyan/s2892/cmos.layout
View File

@ -78,10 +78,10 @@ enumerations
7 9 Fallback_HDD
7 10 Fallback_Floppy
#7 3 ROM
8 0 DDR400
8 1 DDR333
8 2 DDR266
8 3 DDR200
8 0 200Mhz
8 1 166Mhz
8 2 133Mhz
8 3 100Mhz
9 0 off
9 1 87.5%
9 2 75.0%

39
src/mainboard/tyan/s2892/get_bus_conf.c
View File

@ -7,6 +7,7 @@
#include <cpu/amd/dualcore.h>
#endif
#include <cpu/amd/amdk8_sysconf.h>
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
//busnum is default
@ -24,8 +25,7 @@
unsigned apicid_8131_1;
unsigned apicid_8131_2;
unsigned sblk;
unsigned pci1234[] =
unsigned pci1234x[] =
{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not
//You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
0x0000ff0,
@ -37,9 +37,7 @@ unsigned pci1234[] =
// 0x0000ff0,
// 0x0000ff0
};
unsigned hc_possible_num;
unsigned sbdn;
unsigned hcdn[] =
unsigned hcdnx[] =
{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
0x20202020,
0x20202020,
@ -61,23 +59,29 @@ void get_bus_conf(void)
{
unsigned apicid_base;
unsigned sbdn;
device_t dev;
int i;
if(get_bus_conf_done==1) return; //do it only once
if(get_bus_conf_done==1) return; //do it only once
get_bus_conf_done = 1;
get_bus_conf_done = 1;
hc_possible_num = sizeof(pci1234)/sizeof(pci1234[0]);
sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
for(i=0;i<sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i];
}
get_sblk_pci1234();
get_sblk_pci1234();
sbdn = (hcdn[0] & 0xff); // first byte of first chain
sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
sbdn = sysconf.sbdn;
sbdn3 = (hcdn[1] & 0xff); // first byte of second chain
sbdn3 = (sysconf.hcdn[1] & 0xff); // first byte of second chain
// bus_ck804_0 = node_link_to_bus(0, sblk);
bus_ck804_0 = (pci1234[0] >> 16) & 0xff;
bus_ck804_0 = (sysconf.pci1234[0] >> 16) & 0xff;
/* CK804 */
@ -145,16 +149,15 @@ void get_bus_conf(void)
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x0e,0));
if (dev) {
bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_8131_0 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_8131_0++;
bus_isa = bus_8131_0; // incase only one installed
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
}
else {
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn+ 0x0e);
}
bus_8131_0 = (pci1234[1] >> 16) & 0xff;
bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff;
/* 8131-1 */
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0));
if (dev) {

6
src/mainboard/tyan/s2892/irq_tables.c
View File

@ -10,6 +10,8 @@
#include <stdint.h>
#include <arch/pirq_routing.h>
#include <cpu/amd/amdk8_sysconf.h>
static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
uint8_t slot, uint8_t rfu)
@ -39,8 +41,6 @@ extern unsigned char bus_8131_0;//7
extern unsigned char bus_8131_1;//8
extern unsigned char bus_8131_2;//9
extern unsigned sbdn;
extern unsigned hcdn[];
extern unsigned sbdn3;
extern void get_bus_conf(void);
@ -52,11 +52,13 @@ unsigned long write_pirq_routing_table(unsigned long addr)
struct irq_info *pirq_info;
unsigned slot_num;
uint8_t *v;
unsigned sbdn;
uint8_t sum=0;
int i;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
sbdn = sysconf.sbdn;
/* Align the table to be 16 byte aligned. */
addr += 15;

9
src/mainboard/tyan/s2892/mptable.c
View File

@ -4,6 +4,8 @@
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdk8_sysconf.h>
extern unsigned char bus_isa;
extern unsigned char bus_ck804_0; //1
extern unsigned char bus_ck804_1; //2
@ -18,8 +20,6 @@ extern unsigned apicid_ck804;
extern unsigned apicid_8131_1;
extern unsigned apicid_8131_2;
extern unsigned sbdn;
extern unsigned hcdn[];
extern unsigned sbdn3;
@ -29,6 +29,7 @@ void *smp_write_config_table(void *v)
static const char oem[8] = "TYAN ";
static const char productid[12] = "S2892 ";
struct mp_config_table *mc;
unsigned sbdn;
unsigned char bus_num;
int i;
@ -53,6 +54,7 @@ void *smp_write_config_table(void *v)
smp_write_processors(mc);
get_bus_conf();
sbdn = sysconf.sbdn;
/*Bus: Bus ID Type*/
/* define bus and isa numbers */
@ -74,11 +76,12 @@ void *smp_write_config_table(void *v)
smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
}
/* Initialize interrupt mapping*/
dword = 0x0000d218;
pci_write_config32(dev, 0x7c, dword);
dword = 0x12008a00;
pci_write_config32(dev, 0x80, dword);
dword = 0x0000007d;

4
src/mainboard/tyan/s2892/resourcemap.c
View File

@ -258,8 +258,8 @@ static void setup_s2892_resource_map(void)
* This field defines the highest bus number in configuration region i
*/
#if 1
// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003,
// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203,
// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, /* link 0 of cpu 0 --> Nvidia CK 804 Pro */
// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 */
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
#endif

80
src/mainboard/tyan/s2895/Config.lb
View File

@ -2,12 +2,17 @@
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
if USE_FAILOVER_IMAGE
default ROM_SECTION_SIZE = FAILOVER_SIZE
default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
else
default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
else
default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
default ROM_SECTION_OFFSET = 0
end
end
##
@ -16,7 +21,6 @@ end
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_STREAM = 1
##
## Compute where this copy of linuxBIOS will start in the boot rom
@ -31,11 +35,19 @@ default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
##
default XIP_ROM_SIZE=65536
default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
if USE_FAILOVER_IMAGE
default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
else
if USE_FALLBACK_IMAGE
default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
else
default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
end
end
arch i386 end
##
## Build the objects we have code for in this directory.
##
@ -92,9 +104,16 @@ end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
ldscript /cpu/x86/16bit/entry16.lds
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
ldscript /cpu/x86/16bit/entry16.lds
end
else
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
ldscript /cpu/x86/16bit/entry16.lds
end
end
mainboardinit cpu/x86/32bit/entry32.inc
@ -113,12 +132,22 @@ end
##
## Build our reset vector (This is where linuxBIOS is entered)
##
if USE_FALLBACK_IMAGE
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
else
mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds
end
else
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds
end
end
if USE_DCACHE_RAM
@ -136,13 +165,18 @@ ldscript /southbridge/nvidia/ck804/id.lds
##
## ROMSTRAP table for CK804
##
if USE_FALLBACK_IMAGE
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
mainboardinit southbridge/nvidia/ck804/romstrap.inc
ldscript /southbridge/nvidia/ck804/romstrap.lds
end
else
if USE_FALLBACK_IMAGE
mainboardinit southbridge/nvidia/ck804/romstrap.inc
ldscript /southbridge/nvidia/ck804/romstrap.lds
end
end
if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
@ -155,12 +189,20 @@ end
### Things are delicate and we test to see if we should
### failover to another image.
###
if USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
if USE_DCACHE_RAM
else
mainboardinit ./failover.inc
ldscript /arch/i386/lib/failover_failover.lds
end
end
else
if USE_FALLBACK_IMAGE
if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
else
mainboardinit ./failover.inc
end
end
end
##

43
src/mainboard/tyan/s2895/Options.lb
View File

@ -2,6 +2,8 @@ uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses USE_FAILOVER_IMAGE
uses HAVE_FAILOVER_BOOT
uses HAVE_HARD_RESET
uses IRQ_SLOT_COUNT
uses HAVE_OPTION_TABLE
@ -11,6 +13,7 @@ uses CONFIG_LOGICAL_CPUS
uses CONFIG_IOAPIC
uses CONFIG_SMP
uses FALLBACK_SIZE
uses FAILOVER_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
@ -60,6 +63,8 @@ uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
uses CONFIG_USE_INIT
uses SERIAL_CPU_INIT
uses ENABLE_APIC_EXT_ID
uses APIC_ID_OFFSET
uses LIFT_BSP_APIC_ID
@ -69,28 +74,34 @@ uses HT_CHAIN_END_UNITID_BASE
uses SB_HT_CHAIN_ON_BUS0
uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
uses CONFIG_LB_MEM_TOPK
## ROM_SIZE is the size of boot ROM that this board will use.
#512K bytes
#default ROM_SIZE=524288
default ROM_SIZE=524288
#1M bytes
default ROM_SIZE=1048576
#default ROM_SIZE=1048576
##
## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
##
#default FALLBACK_SIZE=131072
#256K
default FALLBACK_SIZE=0x40000
#default FALLBACK_SIZE=0x40000
###
### Build options
###
#FALLBACK: 256K-4K
default FALLBACK_SIZE=0x3f000
#FAILOVER: 4K
default FAILOVER_SIZE=0x01000
#more 1M for pgtbl
default CONFIG_LB_MEM_TOPK=2048
##
## Build code for the fallback boot
##
default HAVE_FALLBACK_BOOT=1
default HAVE_FAILOVER_BOOT=1
##
## Build code to reset the motherboard from linuxBIOS
@ -130,15 +141,14 @@ default CONFIG_MAX_CPUS=4
default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=1
default SERIAL_CPU_INIT=0
#CHIP_NAME ?
#default CONFIG_CHIP_NAME=1
#1G memory hole
default HW_MEM_HOLE_SIZEK=0x100000
#Opteron K8 1G HT Support
default K8_HT_FREQ_1G_SUPPORT=1
##HT Unit ID offset, default is 1, the typical one
default HT_CHAIN_UNITID_BASE=0x0
@ -151,6 +161,9 @@ default SB_HT_CHAIN_ON_BUS0=2
##only offset for SB chain?, default is yes(1)
default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
#Opteron K8 1G HT Support
default K8_HT_FREQ_1G_SUPPORT=1
#VGA
default CONFIG_CONSOLE_VGA=1
default CONFIG_PCI_ROM_RUN=1
@ -163,7 +176,7 @@ default DCACHE_RAM_BASE=0xcf000
default DCACHE_RAM_SIZE=0x1000
default CONFIG_USE_INIT=0
default ENABLE_APIC_EXT_ID=1
default ENABLE_APIC_EXT_ID=0
default APIC_ID_OFFSET=0x10
default LIFT_BSP_APIC_ID=0
@ -201,12 +214,12 @@ default HEAP_SIZE=0x4000
##
## Only use the option table in a normal image
##
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
##
## LinuxBIOS C code runs at this location in RAM
##
default _RAMBASE=0x00004000
default _RAMBASE=0x00100000
##
## Load the payload from the ROM
@ -220,8 +233,8 @@ default CONFIG_ROM_STREAM = 1
##
## The default compiler
##
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
default CC="$(CROSS_COMPILE)gcc-4.0.2 -m32"
default HOSTCC="gcc-4.0.2"
##
## Disable the gdb stub by default

4
src/mainboard/tyan/s2895/auto.c
View File

@ -13,7 +13,7 @@
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/cpu_rev.c"
//#define K8_HT_FREQ_1G_SUPPORT 1
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/nvidia/ck804/ck804_early_smbus.c"
@ -23,7 +23,7 @@
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include <cpu/amd/model_fxx_msr.h>
#include "cpu/amd/model_fxx/model_fxx_msr.h"
#include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"

110
src/mainboard/tyan/s2895/cache_as_ram_auto.c
View File

@ -6,7 +6,7 @@
//#define K8_SCAN_PCI_BUS 1
#define K8_4RANK_DIMM_SUPPORT 1
#define QRANK_DIMM_SUPPORT 1
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
@ -21,30 +21,53 @@
#include <cpu/x86/lapic.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#if USE_FAILOVER_IMAGE==0
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#if 0
static void post_code(uint8_t value) {
#if 1
int i;
for(i=0;i<0x8000;i++) {
outb(value, 0x80);
}
#endif
}
#endif
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/nvidia/ck804/ck804_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
#include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
#define SUPERIO_GPIO_IO_BASE 0x400
#if USE_FAILOVER_IMAGE==0
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
@ -58,9 +81,6 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
#define SUPERIO_GPIO_IO_BASE 0x400
static void sio_gpio_setup(void){
@ -94,6 +114,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/dualcore/dualcore.c"
#define CK804_NUM 2
#define CK804B_BUSN 0x80
#define CK804_USE_NIC 1
#define CK804_USE_ACI 1
@ -116,8 +137,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c"
#endif
#if USE_FALLBACK_IMAGE == 1
#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@ -133,7 +155,7 @@ static void sio_setup(void)
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
byte |= 0x20;
pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
@ -141,13 +163,14 @@ static void sio_setup(void)
dword |= (1<<29)|(1<<0);
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
#if 1
lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xa4);
dword |= (1<<16);
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
value &= 0xbf;
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
#endif
}
@ -175,6 +198,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
ck804_enable_rom();
/* Is this a deliberate reset by the bios */
// post_code(0x22);
if (bios_reset_detected() && last_boot_normal_x) {
goto normal_image;
}
@ -186,28 +210,43 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
goto fallback_image;
}
normal_image:
// post_code(0x23);
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
);
fallback_image:
// post_code(0x25);
#if HAVE_FAILOVER_BOOT==1
__asm__ volatile ("jmp __fallback_image"
: /* outputs */
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
)
#endif
;
}
#endif
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
#if USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#if HAVE_FAILOVER_BOOT==1
#if USE_FAILOVER_IMAGE==1
failover_process(bist, cpu_init_detectedx);
#else
real_main(bist, cpu_init_detectedx);
#endif
#else
#if USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
}
#if USE_FAILOVER_IMAGE==0
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
@ -229,6 +268,8 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
bsp_apicid = init_cpus(cpu_init_detectedx);
}
// post_code(0x32);
lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
@ -236,15 +277,21 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
setup_s2895_resource_map();
sio_gpio_setup();
setup_mb_resource_map();
#if 0
dump_pci_device(PCI_DEV(0, 0x18, 0));
dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif
needs_reset = setup_coherent_ht_domain();
wait_all_core0_started();
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS==1
// It is said that we should start core1 after all core0 launched
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
wait_all_other_cores_started(bsp_apicid);
#endif
needs_reset |= ht_setup_chains_x();
@ -253,7 +300,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (needs_reset) {
print_info("ht reset -\r\n");
soft_reset();
// soft_reset();
}
allow_all_aps_stop(bsp_apicid);
@ -263,9 +310,24 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
fill_mem_ctrl(nodes, ctrl, spd_addr);
enable_smbus();
#if 0
dump_spd_registers(&cpu[0]);
#endif
#if 0
dump_smbus_registers();
#endif
memreset_setup();
sdram_initialize(nodes, ctrl);
#if 0
print_pci_devices();
#endif
#if 0
dump_pci_devices();
#endif
post_cache_as_ram();
}
#endif

8
src/mainboard/tyan/s2895/cmos.layout
View File

@ -78,10 +78,10 @@ enumerations
7 9 Fallback_HDD
7 10 Fallback_Floppy
#7 3 ROM
8 0 DDR400
8 1 DDR333
8 2 DDR266
8 3 DDR200
8 0 200Mhz
8 1 166Mhz
8 2 133Mhz
8 3 100Mhz
9 0 off
9 1 87.5%
9 2 75.0%

39
src/mainboard/tyan/s2895/get_bus_conf.c
View File

@ -7,6 +7,8 @@
#include <cpu/amd/dualcore.h>
#endif
#include <cpu/amd/amdk8_sysconf.h>
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
//busnum is default
@ -31,8 +33,7 @@
unsigned apicid_8131_2;
unsigned apicid_ck804b;
unsigned sblk;
unsigned pci1234[] =
unsigned pci1234x[] =
{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not
//You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
0x0000ff0,
@ -44,9 +45,7 @@ unsigned pci1234[] =
// 0x0000ff0,
// 0x0000ff0
};
unsigned hc_possible_num;
unsigned sbdn;
unsigned hcdn[] =
unsigned hcdnx[] =
{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
0x20202020,
0x20202020,
@ -68,25 +67,31 @@ void get_bus_conf(void)
{
unsigned apicid_base;
unsigned sbdn;
device_t dev;
int i;
if(get_bus_conf_done==1) return; //do it only once
if(get_bus_conf_done==1) return; //do it only once
get_bus_conf_done = 1;
get_bus_conf_done = 1;
hc_possible_num = sizeof(pci1234)/sizeof(pci1234[0]);
sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
for(i=0;i<sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i];
}
get_sblk_pci1234();
get_sblk_pci1234();
sbdn = (hcdn[0] & 0xff); // first byte of first chain
sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
sbdn = sysconf.sbdn;
sbdn3 = (hcdn[1] & 0xff);
sbdn3 = (sysconf.hcdn[1] & 0xff);
sbdnb = (hcdn[2] & 0xff); // first byte of second chain
sbdnb = (sysconf.hcdn[2] & 0xff); // first byte of second chain
// bus_ck804_0 = node_link_to_bus(0, sblk);
bus_ck804_0 = (pci1234[0] >> 16) & 0xff;
bus_ck804_0 = (sysconf.pci1234[0] >> 16) & 0xff;
/* CK804 */
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09,0));
@ -158,7 +163,7 @@ void get_bus_conf(void)
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn+ 0x0e);
}
bus_8131_0 = (pci1234[1] >> 16) & 0xff;
bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff;
/* 8131-1 */
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0));
if (dev) {
@ -187,8 +192,8 @@ void get_bus_conf(void)
/* CK804b */
if(pci1234[2] & 0xf) { //if the second cpu is installed
bus_ck804b_0 = (pci1234[2]>>16) & 0xff;
if(sysconf.pci1234[2] & 0x0f) { //if the second cpu is installed
bus_ck804b_0 = (sysconf.pci1234[2]>>16) & 0xff;
#if 0
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x09,0));
if (dev) {

9
src/mainboard/tyan/s2895/irq_tables.c
View File

@ -10,6 +10,8 @@
#include <stdint.h>
#include <arch/pirq_routing.h>
#include <cpu/amd/amdk8_sysconf.h>
static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
uint8_t slot, uint8_t rfu)
@ -44,10 +46,7 @@ extern unsigned char bus_ck804b_3;//d
extern unsigned char bus_ck804b_4;//e
extern unsigned char bus_ck804b_5;//f
extern unsigned pci1234[];
extern unsigned sbdn;
extern unsigned hcdn[];
extern unsigned sbdn3;
extern unsigned sbdnb;
@ -58,11 +57,13 @@ unsigned long write_pirq_routing_table(unsigned long addr)
struct irq_info *pirq_info;
unsigned slot_num;
uint8_t *v;
unsigned sbdn;
uint8_t sum=0;
int i;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
sbdn = sysconf.sbdn;
/* Align the table to be 16 byte aligned. */
addr += 15;
@ -98,7 +99,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++;
if(pci1234[2] & 0xf) {
if(sysconf.pci1234[2] & 0xf) {
//second pci beidge
write_pirq_info(pirq_info, bus_ck804b_0, ((sbdnb+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x0, 0);
pirq_info++; slot_num++;

13
src/mainboard/tyan/s2895/mptable.c
View File

@ -4,6 +4,8 @@
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdk8_sysconf.h>
extern unsigned char bus_isa;
extern unsigned char bus_ck804_0; //1
extern unsigned char bus_ck804_1; //2
@ -25,10 +27,6 @@ extern unsigned apicid_8131_1;
extern unsigned apicid_8131_2;
extern unsigned apicid_ck804b;
extern unsigned pci1234[];
extern unsigned sbdn;
extern unsigned hcdn[];
extern unsigned sbdn3;
extern unsigned sbdnb;
@ -38,6 +36,7 @@ void *smp_write_config_table(void *v)
static const char oem[8] = "TYAN ";
static const char productid[12] = "S2895 ";
struct mp_config_table *mc;
unsigned sbdn;
unsigned char bus_num;
int i;
@ -62,6 +61,7 @@ void *smp_write_config_table(void *v)
smp_write_processors(mc);
get_bus_conf();
sbdn = sysconf.sbdn;
/*Bus: Bus ID Type*/
/* define bus and isa numbers */
@ -83,6 +83,7 @@ void *smp_write_config_table(void *v)
smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
}
/* Initialize interrupt mapping*/
dword = 0x0000d218;
pci_write_config32(dev, 0x7c, dword);
@ -110,7 +111,7 @@ void *smp_write_config_table(void *v)
}
}
if(pci1234[2] & 0xf) {
if(sysconf.pci1234[2] & 0xf) {
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x1,0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
@ -181,7 +182,7 @@ void *smp_write_config_table(void *v)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|i, apicid_ck804, 0x10 + (0+i)%4);
}
if(pci1234[2] & 0xf) {
if(sysconf.pci1234[2] & 0xf) {
//Onboard ck804b NIC
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_0, ((sbdnb+0x0a)<<2)|0, apicid_ck804b, 0x15);//24+4+4+21=53

12
src/mainboard/tyan/s2895/resourcemap.c
View File

@ -3,7 +3,7 @@
*
*/
static void setup_s2895_resource_map(void)
static void setup_mb_resource_map(void)
{
static const unsigned int register_values[] = {
/* Careful set limit registers before base registers which contain the enables */
@ -183,7 +183,7 @@ static void setup_s2895_resource_map(void)
* [31:25] Reserved
*/
PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000,
PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x01fff001,
PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x01fff001, // need to talk to ANALOG of second CK804 to release PCI E reset
PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
@ -253,10 +253,10 @@ static void setup_s2895_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i
*/
PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003,
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203,
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0xff800013,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, /* link 0 of cpu 0 --> Nvidia CK 804 Pro */
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 */
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0xff800013, /* link 0 of cpu 1 --> Nvidia CK 804 Slave */
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, /*113 link 1 of cpu 1 --> HT connector */
};

22
targets/tyan/s2895/Config.lb
View File

@ -8,13 +8,14 @@ mainboard tyan/s2895
# Tyan s2895
romimage "normal"
# 48K for SCSI FW
# option ROM_SIZE = 512*1024-48*1024
# option ROM_SIZE = 475136
# 48K for SCSI FW and 48K for ATI ROM
# option ROM_SIZE = 512*1024-48*1024-48*1024
# option ROM_SIZE = 425984
# 64K for Etherboot
# option ROM_SIZE = 512*1024-64*1024
# option ROM_SIZE = 458752
# 64K for NIC option 48K for Raid option rom
# option ROM_SIZE = 512*1024-64*1024-48*1024
# option ROM_SIZE = 409600
option USE_FAILOVER_IMAGE=0
option USE_FALLBACK_IMAGE=0
# option ROM_IMAGE_SIZE=0x11800
# option ROM_IMAGE_SIZE=0x13800
@ -44,6 +45,7 @@ romimage "normal"
end
romimage "fallback"
option USE_FAILOVER_IMAGE=0
option USE_FALLBACK_IMAGE=1
# option ROM_IMAGE_SIZE=0x11800
# option ROM_IMAGE_SIZE=0x13800
@ -69,4 +71,14 @@ romimage "fallback"
# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
end
buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
romimage "failover"
option USE_FAILOVER_IMAGE=1
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=FAILOVER_SIZE
option XIP_ROM_SIZE=FAILOVER_SIZE
option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
end
buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover"
#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"