From 6d81b15bbe99a607c74021b28d4c8e7ca37e1bf3 Mon Sep 17 00:00:00 2001 From: Krystian Hebel Date: Tue, 26 Feb 2019 12:02:16 +0100 Subject: [PATCH] superio/ite/it8613e: add support for ITE IT8613E This change adds support for the SuperIO chip IT8613E. This chip uses FANs 2-5 and has SmartGuardian always enabled (no ON/OFF control) so it relies on support in common ITE code. LDNs were taken from IT8613E Preliminary Specification V0.3. Change-Id: I73c083b7019163c1203a5aabbef7d9d8f5ccb16a Signed-off-by: Krystian Hebel Reviewed-on: https://review.coreboot.org/c/coreboot/+/31617 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/superio/ite/it8613e/Kconfig | 27 +++++++++ src/superio/ite/it8613e/Makefile.inc | 19 +++++++ src/superio/ite/it8613e/chip.h | 27 +++++++++ src/superio/ite/it8613e/it8613e.h | 48 ++++++++++++++++ src/superio/ite/it8613e/superio.c | 85 ++++++++++++++++++++++++++++ 5 files changed, 206 insertions(+) create mode 100644 src/superio/ite/it8613e/Kconfig create mode 100644 src/superio/ite/it8613e/Makefile.inc create mode 100644 src/superio/ite/it8613e/chip.h create mode 100644 src/superio/ite/it8613e/it8613e.h create mode 100644 src/superio/ite/it8613e/superio.c diff --git a/src/superio/ite/it8613e/Kconfig b/src/superio/ite/it8613e/Kconfig new file mode 100644 index 0000000000..f09cac2fa8 --- /dev/null +++ b/src/superio/ite/it8613e/Kconfig @@ -0,0 +1,27 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2014 Edward O'Callaghan +## Copyright (C) 2017 Gergely Kiss +## Copyright (C) 2018 Kevin Cody-Little +## Copyright (C) 2019 Protectli +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SUPERIO_ITE_IT8613E + bool + select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_ENV_CTRL + select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 + select SUPERIO_ITE_ENV_CTRL_8BIT_PWM + select SUPERIO_ITE_ENV_CTRL_5FANS + select SUPERIO_ITE_ENV_CTRL_NO_ONOFF diff --git a/src/superio/ite/it8613e/Makefile.inc b/src/superio/ite/it8613e/Makefile.inc new file mode 100644 index 0000000000..75ab26bc5e --- /dev/null +++ b/src/superio/ite/it8613e/Makefile.inc @@ -0,0 +1,19 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2006 Uwe Hermann +## Copyright (C) 2017 Gergely Kiss +## Copyright (C) 2019 Protectli +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SUPERIO_ITE_IT8613E) += superio.c diff --git a/src/superio/ite/it8613e/chip.h b/src/superio/ite/it8613e/chip.h new file mode 100644 index 0000000000..65875c8fc2 --- /dev/null +++ b/src/superio/ite/it8613e/chip.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan + * Copyright (C) 2019 Protectli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_ITE_IT8613E_CHIP_H +#define SUPERIO_ITE_IT8613E_CHIP_H + +#include + +struct superio_ite_it8613e_config { + struct ite_ec_config ec; +}; + +#endif /* SUPERIO_ITE_IT8613E_CHIP_H */ diff --git a/src/superio/ite/it8613e/it8613e.h b/src/superio/ite/it8613e/it8613e.h new file mode 100644 index 0000000000..890c24925d --- /dev/null +++ b/src/superio/ite/it8613e/it8613e.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Uwe Hermann + * Copyright (C) 2017 Gergely Kiss + * Copyright (C) 2019 Protectli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_ITE_IT8613E_H +#define SUPERIO_ITE_IT8613E_H + +/* + * IT8613 supports 2 clock inputs: PCICLK and CLKIN. Multiple registers need + * to be set to choose proper source. PCICLK is required for LPC. + * + * In the table below PD means pull-down, X - don't care. + * + * |-------------------------------------------------------------------| + * | CLKIN | PCICLK | LDN7\ | GBL\ | LDN7\ | LDN7\ | GBL\ | + * | | | 71h[3] | 23h[3] | 2Dh[2] | 2Dh[1] | 23h[0] | + * |--------+--------+---------+---------+---------+---------+---------| + * | PD | 33 MHz | X | 0 | 0 | 0 | 0 | + * | PD | 24 MHz | 1 | 1 | X | 0 | 1 | + * | PD | 25 MHz | X | 0 | 1 | 0 | 0 | + * | 24 MHz | X | 0 | 1 | X | 0 | 1 | + * | 48 MHz | X | 0 | 1 | X | 0 | 0 | + * |-------------------------------------------------------------------| + * + */ + +#define IT8613E_SP1 0x01 /* Com1 */ +#define IT8613E_EC 0x04 /* Environment controller */ +#define IT8613E_KBCK 0x05 /* PS/2 keyboard */ +#define IT8613E_KBCM 0x06 /* PS/2 mouse */ +#define IT8613E_GPIO 0x07 /* GPIO */ +#define IT8613E_CIR 0x0a /* Consumer Infrared */ + +#endif /* SUPERIO_ITE_IT8613E_H */ diff --git a/src/superio/ite/it8613e/superio.c b/src/superio/ite/it8613e/superio.c new file mode 100644 index 0000000000..7a4e336278 --- /dev/null +++ b/src/superio/ite/it8613e/superio.c @@ -0,0 +1,85 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Uwe Hermann + * Copyright (C) 2007 Philipp Degler + * Copyright (C) 2017 Gergely Kiss + * Copyright (C) 2019 Protectli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#include "chip.h" +#include "it8613e.h" + +static void it8613e_init(struct device *dev) +{ + const struct superio_ite_it8613e_config *conf = dev->chip_info; + const struct resource *res; + + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + case IT8613E_EC: + res = find_resource(dev, PNP_IDX_IO0); + if (!conf || !res) + break; + ite_ec_init(res->base, &conf->ec); + break; + case IT8613E_KBCK: + pc_keyboard_init(NO_AUX_DEVICE); + break; + case IT8613E_KBCM: + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = it8613e_init, + .ops_pnp_mode = &pnp_conf_mode_870155_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + /* Serial Port 1 */ + { NULL, IT8613E_SP1, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0x0ff8, }, + /* Environmental Controller */ + { NULL, IT8613E_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0ff8, 0x0ff8, }, + /* KBC Keyboard */ + { NULL, IT8613E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0, + 0x0fff, 0x0fff, }, + /* KBC Mouse */ + { NULL, IT8613E_KBCM, PNP_IRQ0 | PNP_MSC0, }, + /* GPIO */ + { NULL, IT8613E_GPIO, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0ffc, 0x0ff8, }, + /* Consumer Infrared */ + { NULL, IT8613E_CIR, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0x0ff8, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_ite_it8613e_ops = { + CHIP_NAME("ITE IT8613E Super I/O") + .enable_dev = enable_dev, +};