Kconfig: Add choice of framebuffer mode

Rename `FRAMEBUFFER_KEEP_VESA_MODE` to `LINEAR_FRAMEBUFFER` and put
it together with new `VGA_TEXT_FRAMEBUFFER` into a choice. There are
two versions of `LINEAR_FRAMEBUFFER` that differ only in the prompt
and help text (one for `HAVE_VBE_LINEAR_FRAMEBUFFER` and one for
`HAVE_LINEAR_FRAMEBUFFER`). Due to `kconfig_lint` we have to model
that with additional symbols.

Change-Id: I9144351491a14d9bb5e650c14933b646bc83fab0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/19804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Nico Huber 2017-05-20 16:46:01 +02:00 committed by Martin Roth
parent 49d99fcebc
commit 6d8266b91d
14 changed files with 149 additions and 108 deletions

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@ -2,5 +2,5 @@ CONFIG_COLLECT_TIMESTAMPS=y
# CONFIG_POST_IO is not set
# CONFIG_POST_DEVICE is not set
CONFIG_CONSOLE_POST=y
CONFIG_FRAMEBUFFER_KEEP_VESA_MODE=y
CONFIG_LINEAR_FRAMEBUFFER=y
# CONFIG_CONSOLE_SERIAL is not set

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@ -54,7 +54,7 @@ config SEABIOS_THREAD_OPTIONROMS
config SEABIOS_VGA_COREBOOT
prompt "Include generated option rom that implements legacy VGA BIOS compatibility"
default y if !VENDOR_EMULATION
depends on !VGA_BIOS && MAINBOARD_DO_NATIVE_VGA_INIT
depends on !(VGA_BIOS || VGA_ROM_RUN) && (VGA_TEXT_FRAMEBUFFER || LINEAR_FRAMEBUFFER)
bool
help
Coreboot can initialize the GPU of some mainboards.

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@ -63,7 +63,7 @@ config MAINBOARD_USE_LIBGFXINIT
select HAVE_VGA_TEXT_FRAMEBUFFER
select HAVE_LINEAR_FRAMEBUFFER
select RAMSTAGE_LIBHWBASE
select VGA if !FRAMEBUFFER_KEEP_VESA_MODE
select VGA if VGA_TEXT_FRAMEBUFFER
select NO_EDID_FILL_FB
default n
help
@ -539,16 +539,44 @@ config FRAMEBUFFER_VESA_MODE
default 0x11B if FRAMEBUFFER_VESA_MODE_11B
default 0x117 if FRAMEBUFFER_VESA_MODE_USER
config FRAMEBUFFER_KEEP_VESA_MODE
prompt "Keep VESA framebuffer"
bool
depends on HAVE_VGA_TEXT_FRAMEBUFFER && (HAVE_VBE_LINEAR_FRAMEBUFFER || HAVE_LINEAR_FRAMEBUFFER)
choice
prompt "Framebuffer mode"
default VGA_TEXT_FRAMEBUFFER
config VGA_TEXT_FRAMEBUFFER
bool "Legacy VGA text mode"
depends on HAVE_VGA_TEXT_FRAMEBUFFER
help
If this option is enabled, coreboot will initialize graphics in
legacy VGA text mode or, if a VGA BIOS is used and a VESA mode set,
switch to text mode before handing control to a payload.
config VBE_LINEAR_FRAMEBUFFER
bool "VESA framebuffer"
depends on HAVE_VBE_LINEAR_FRAMEBUFFER
help
This option keeps the framebuffer mode set after coreboot finishes
execution. If this option is enabled, coreboot will pass a
framebuffer entry in its coreboot table and the payload will need a
framebuffer driver. If this option is disabled, coreboot will switch
back to text mode before handing control to a payload.
compatible driver.
config GENERIC_LINEAR_FRAMEBUFFER
bool "Linear \"high-resolution\" framebuffer"
depends on HAVE_LINEAR_FRAMEBUFFER
help
This option enables a high-resolution, linear framebuffer. If this
option is enabled, coreboot will pass a framebuffer entry in its
coreboot table and the payload will need a compatible driver.
endchoice
# Workaround to have LINEAR_FRAMEBUFFER set in both cases
# VBE_LINEAR_FRAMEBUFFER and GENERIC_LINEAR_FRAMEBUFFER.
# `kconfig_lint` doesn't let us use the same name with
# different texts in the choice above.
config LINEAR_FRAMEBUFFER
def_bool y
depends on VBE_LINEAR_FRAMEBUFFER || GENERIC_LINEAR_FRAMEBUFFER
config BOOTSPLASH
prompt "Show graphical bootsplash"

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@ -16,11 +16,11 @@ config DRIVERS_EMULATION_QEMU_BOCHS
config DRIVERS_EMULATION_QEMU_BOCHS_XRES
int "bochs vga xres"
default 800
depends on FRAMEBUFFER_KEEP_VESA_MODE
depends on LINEAR_FRAMEBUFFER
depends on DRIVERS_EMULATION_QEMU_BOCHS
config DRIVERS_EMULATION_QEMU_BOCHS_YRES
int "bochs vga yres"
default 600
depends on FRAMEBUFFER_KEEP_VESA_MODE
depends on LINEAR_FRAMEBUFFER
depends on DRIVERS_EMULATION_QEMU_BOCHS

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@ -41,7 +41,6 @@
#define VBE_DISPI_LFB_ENABLED 0x40
#define VBE_DISPI_NOCLEARMEM 0x80
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
static int width = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_XRES;
static int height = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_YRES;
@ -56,11 +55,9 @@ static int bochs_read(int index)
outw(index, VBE_DISPI_IOPORT_INDEX);
return inw(VBE_DISPI_IOPORT_DATA);
}
#endif
static void bochs_init(struct device *dev)
static void bochs_init_linear_fb(struct device *dev)
{
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
struct edid edid;
int id, mem, bar;
u32 addr;
@ -115,10 +112,20 @@ static void bochs_init(struct device *dev)
edid.panel_bits_per_pixel = 24;
edid_set_framebuffer_bits_per_pixel(&edid, 32, 0);
set_vbe_mode_info_valid(&edid, addr);
#else
}
static void bochs_init_text_mode(struct device *dev)
{
vga_misc_write(0x1);
vga_textmode_init();
#endif
}
static void bochs_init(struct device *dev)
{
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER))
bochs_init_linear_fb(dev);
else if (IS_ENABLED(CONFIG_VGA_TEXT_FRAMEBUFFER))
bochs_init_text_mode(dev);
}
static struct device_operations qemu_graph_ops = {

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@ -31,11 +31,9 @@
#include <pc80/vga.h>
#include <pc80/vga_io.h>
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
static int width = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_XRES;
static int height = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_YRES;
static u32 addr = 0;
#endif
enum
{
@ -194,7 +192,6 @@ enum
#define CIRRUS_SR_EXTENDED_MODE_32BPP 0x08
#define CIRRUS_HIDDEN_DAC_888COLOR 0xc5
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
static void
write_hidden_dac (uint8_t data)
{
@ -205,11 +202,9 @@ write_hidden_dac (uint8_t data)
inb (0x3c6);
outb (data, 0x3c6);
}
#endif
static void cirrus_init(struct device *dev)
static void cirrus_init_linear_fb(struct device *dev)
{
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
uint8_t cr_ext, cr_overlay;
unsigned pitch = (width * 4) / VGA_CR_PITCH_DIVISOR;
uint8_t sr_ext = 0, hidden_dac = 0;
@ -334,11 +329,20 @@ static void cirrus_init(struct device *dev)
edid.panel_bits_per_pixel = 24;
edid_set_framebuffer_bits_per_pixel(&edid, 32, 0);
set_vbe_mode_info_valid(&edid, addr);
#else
vga_misc_write(0x1);
}
static void cirrus_init_text_mode(struct device *dev)
{
vga_misc_write(0x1);
vga_textmode_init();
#endif
}
static void cirrus_init(struct device *dev)
{
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER))
cirrus_init_linear_fb(dev);
else if (IS_ENABLED(CONFIG_VGA_TEXT_FRAMEBUFFER))
cirrus_init_text_mode(dev);
}
static struct device_operations qemu_cirrus_graph_ops = {

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@ -39,7 +39,7 @@ CONFIG_GFX_GMA_DEFAULT_MMIO := 0 # dummy, will be overwritten at runtime
subdirs-y += ../../../../3rdparty/libgfxinit
ramstage-y += gma.ads
ifeq ($(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE),y)
ifeq ($(CONFIG_LINEAR_FRAMEBUFFER),y)
ramstage-y += hires_fb/gma.adb
else
ramstage-y += text_fb/gma.adb

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@ -6,11 +6,13 @@ void __attribute__((weak)) set_boot_successful(void) { }
void boot_successful(void)
{
#if CONFIG_FRAMEBUFFER_SET_VESA_MODE && !CONFIG_FRAMEBUFFER_KEEP_VESA_MODE
void vbe_textmode_console(void);
if (IS_ENABLED(CONFIG_FRAMEBUFFER_SET_VESA_MODE) &&
IS_ENABLED(CONFIG_VGA_TEXT_FRAMEBUFFER)) {
void vbe_textmode_console(void);
vbe_textmode_console();
}
vbe_textmode_console();
#endif
/* Remember this was a successful boot */
set_boot_successful();

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@ -109,7 +109,7 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info,
hfront_porch = mode->hso;
vfront_porch = mode->vso;
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
vga_sr_write(1, 1);
vga_sr_write(0x2, 0xf);
vga_sr_write(0x3, 0x0);
@ -263,7 +263,7 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info,
write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
write32(mmio + PF_WIN_POS(0), 0);
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
write32(mmio + PIPESRC(0), ((hactive - 1) << 16)
| (vactive - 1));
write32(mmio + PF_CTL(0), 0);
@ -281,7 +281,7 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info,
write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
write32(mmio + VGACNTRL, VGA_DISP_DISABLE);
write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE
| DISPPLANE_BGRX888);
@ -307,7 +307,7 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info,
write32(mmio + DEIIR, 0xffffffff);
write32(mmio + SDEIIR, 0xffffffff);
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
memset((void *) lfb, 0,
edid->x_resolution * edid->y_resolution * 4);
set_vbe_mode_info_valid(edid, lfb);
@ -390,7 +390,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info,
vfront_porch = mode->vso;
target_frequency = mode->pixel_clock;
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
vga_sr_write(1, 1);
vga_sr_write(0x2, 0xf);
vga_sr_write(0x3, 0x0);
@ -520,7 +520,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info,
write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
write32(mmio + PF_WIN_POS(0), 0);
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
write32(mmio + PIPESRC(0), ((hactive - 1) << 16)
| (vactive - 1));
write32(mmio + PF_CTL(0), 0);
@ -539,7 +539,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info,
write32(mmio + PIPECONF(0), PIPECONF_ENABLE
| PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
write32(mmio + VGACNTRL, VGA_DISP_DISABLE);
write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE
| DISPPLANE_BGRX888);
@ -569,7 +569,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info,
write32(mmio + DEIIR, 0xffffffff);
write32(mmio + SDEIIR, 0xffffffff);
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
memset((void *) lfb, 0,
edid->x_resolution * edid->y_resolution * 4);
set_vbe_mode_info_valid(edid, lfb);

View File

@ -217,7 +217,7 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf,
BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) /
(pixel_n + 2) / (pixel_p1 * pixel_p2));
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
/* Disable panel fitter (we're in native resolution). */
write32(mmiobase + PF_CTL(0), 0);
write32(mmiobase + PF_WIN_SZ(0), 0);
@ -280,7 +280,7 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf,
((vactive + bottom_border + vfront_porch + vsync - 1) << 16)
| (vactive + bottom_border + vfront_porch - 1));
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
write32(mmiobase + PIPESRC(1), ((hactive - 1) << 16)
| (vactive - 1));
} else {
@ -359,7 +359,7 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf,
else
printk(BIOS_ERR, "ERROR: GTT is still Disabled!!!\n");
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
printk(BIOS_SPEW, "memset %p to 0x00 for %d bytes\n",
(void *)pgfx, hactive * vactive * 4);
memset((void *)pgfx, 0x00, hactive * vactive * 4);

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@ -724,32 +724,33 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
target_frequency = mode->lvds_dual_channel ? mode->pixel_clock
: (2 * mode->pixel_clock);
vga_textmode_init();
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
vga_sr_write(1, 1);
vga_sr_write(0x2, 0xf);
vga_sr_write(0x3, 0x0);
vga_sr_write(0x4, 0xe);
vga_gr_write(0, 0x0);
vga_gr_write(1, 0x0);
vga_gr_write(2, 0x0);
vga_gr_write(3, 0x0);
vga_gr_write(4, 0x0);
vga_gr_write(5, 0x0);
vga_gr_write(6, 0x5);
vga_gr_write(7, 0xf);
vga_gr_write(0x10, 0x1);
vga_gr_write(0x11, 0);
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
vga_sr_write(1, 1);
vga_sr_write(0x2, 0xf);
vga_sr_write(0x3, 0x0);
vga_sr_write(0x4, 0xe);
vga_gr_write(0, 0x0);
vga_gr_write(1, 0x0);
vga_gr_write(2, 0x0);
vga_gr_write(3, 0x0);
vga_gr_write(4, 0x0);
vga_gr_write(5, 0x0);
vga_gr_write(6, 0x5);
vga_gr_write(7, 0xf);
vga_gr_write(0x10, 0x1);
vga_gr_write(0x11, 0);
edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;
edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;
write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888);
write32(mmio + DSPADDR(0), 0);
write32(mmio + DSPSTRIDE(0), edid.bytes_per_line);
write32(mmio + DSPSURF(0), 0);
for (i = 0; i < 0x100; i++)
write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);
#endif
write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888);
write32(mmio + DSPADDR(0), 0);
write32(mmio + DSPSTRIDE(0), edid.bytes_per_line);
write32(mmio + DSPSURF(0), 0);
for (i = 0; i < 0x100; i++)
write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);
}
/* Find suitable divisors. */
for (candp1 = 1; candp1 <= 8; candp1++) {
@ -883,15 +884,15 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
write32(mmio + PF_WIN_POS(0), 0);
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1));
write32(mmio + PF_CTL(0),0);
write32(mmio + PF_WIN_SZ(0), 0);
#else
write32(mmio + PIPESRC(0), (639 << 16) | 399);
write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
#endif
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
write32(mmio + PIPESRC(0), (hactive - 1) << 16 | (vactive - 1));
write32(mmio + PF_CTL(0), 0);
write32(mmio + PF_WIN_SZ(0), 0);
} else {
write32(mmio + PIPESRC(0), (639 << 16) | 399);
write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3);
write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
}
mdelay(1);
@ -911,17 +912,18 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
write32(mmio + CPU_VGACNTRL, 0x20298e | VGA_DISP_DISABLE);
#else
write32(mmio + CPU_VGACNTRL, 0x20298e);
#endif
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER))
write32(mmio + CPU_VGACNTRL, 0x20298e | VGA_DISP_DISABLE);
else
write32(mmio + CPU_VGACNTRL, 0x20298e);
train_link(mmio);
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
mdelay(1);
#endif
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
write32(mmio + DSPCNTR(0),
DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
mdelay(1);
}
write32(mmio + TRANS_HTOTAL(0),
((hactive + right_border + hblank - 1) << 16)
@ -946,11 +948,8 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
write32(mmio + 0x00060100, 0xb01c4000);
write32(mmio + 0x000f000c, 0xb01a2050);
mdelay(1);
write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
| TRANS_STATE_MASK
#endif
);
write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC |
(IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER) ? TRANS_STATE_MASK : 0));
write32(mmio + PCH_LVDS,
LVDS_PORT_ENABLE
| (hpolarity << 20) | (vpolarity << 21)
@ -988,10 +987,11 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
write32(mmio + 0x0004f04c, 0x7f7f0000);
write32(mmio + 0x0004f054, 0x0000020d);
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4);
set_vbe_mode_info_valid(&edid, lfb);
#endif
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
memset((void *)lfb, 0,
edid.x_resolution * edid.y_resolution * 4);
set_vbe_mode_info_valid(&edid, lfb);
}
}
#endif

View File

@ -217,7 +217,7 @@ int i915lightup_ivy(const struct i915_gpu_controller_info *info,
u32 pixel_m2 = 1;
vga_textmode_init();
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
vga_sr_write(1, 1);
vga_sr_write(0x2, 0xf);
vga_sr_write(0x3, 0x0);
@ -387,7 +387,7 @@ int i915lightup_ivy(const struct i915_gpu_controller_info *info,
write32(mmio + 0xf0008, 0);
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1));
write32(mmio + PF_CTL(0),0);
write32(mmio + PF_WIN_SZ(0), 0);
@ -408,7 +408,7 @@ int i915lightup_ivy(const struct i915_gpu_controller_info *info,
link_train(mmio);
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE))
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER))
write32(mmio+CPU_VGACNTRL,0x298e | VGA_DISP_DISABLE);
else
write32(mmio+CPU_VGACNTRL,0x298e);
@ -419,7 +419,7 @@ int i915lightup_ivy(const struct i915_gpu_controller_info *info,
mdelay(1);
read32(mmio + 0x000f0014); // = 0x00000600
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE
| DISPPLANE_BGRX888);
mdelay(1);
@ -451,7 +451,7 @@ int i915lightup_ivy(const struct i915_gpu_controller_info *info,
mdelay(1);
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE))
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER))
write32(mmio + PCH_TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC
| TRANS_STATE_MASK);
else
@ -490,7 +490,7 @@ int i915lightup_ivy(const struct i915_gpu_controller_info *info,
write32(mmio + DEIIR, 0xffffffff);
write32(mmio + SDEIIR, 0xffffffff);
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
memset ((void *) lfb, 0, edid.x_resolution
* edid.y_resolution * 4);
set_vbe_mode_info_valid(&edid, lfb);

View File

@ -200,7 +200,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
target_frequency = mode->lvds_dual_channel ? mode->pixel_clock
: (2 * mode->pixel_clock);
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
vga_sr_write(1, 1);
vga_sr_write(0x2, 0xf);
vga_sr_write(0x3, 0x0);
@ -361,7 +361,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
write32(mmio + PF_WIN_POS(0), 0);
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1));
write32(mmio + PF_CTL(0),0);
write32(mmio + PF_WIN_SZ(0), 0);
@ -388,14 +388,14 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE))
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER))
write32(mmio + CPU_VGACNTRL, 0x20298e | VGA_DISP_DISABLE);
else
write32(mmio + CPU_VGACNTRL, 0x20298e);
train_link(mmio);
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
mdelay(1);
}
@ -424,7 +424,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
write32(mmio + 0x000f000c, 0x801a2350);
mdelay(1);
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE))
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER))
write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC
| TRANS_STATE_MASK);
else
@ -462,7 +462,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
write32(mmio + DEIIR, 0xffffffff);
write32(mmio + SDEIIR, 0xffffffff);
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
memset ((void *) lfb, 0, edid.x_resolution
* edid.y_resolution * 4);
set_vbe_mode_info_valid(&edid, lfb);

View File

@ -143,7 +143,7 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info,
} else
printk(BIOS_DEBUG, "EDID is null, using 640 x 480 @ 60Hz mode");
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
vga_sr_write(1, 1);
vga_sr_write(0x2, 0xf);
vga_sr_write(0x3, 0x0);
@ -274,7 +274,7 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info,
write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
write32(mmio + PF_WIN_POS(0), 0);
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
write32(mmio + PIPESRC(0), ((hactive - 1) << 16)
| (vactive - 1));
write32(mmio + PF_CTL(0), 0);
@ -293,7 +293,7 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info,
write32(mmio + PIPECONF(0), PIPECONF_ENABLE
| PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
write32(mmio + VGACNTRL, VGA_DISP_DISABLE);
write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE
| DISPPLANE_BGRX888);
@ -323,7 +323,7 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info,
write32(mmio + DEIIR, 0xffffffff);
write32(mmio + SDEIIR, 0xffffffff);
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
memset((void *) lfb, 0,
hactive * vactive * 4);
set_vbe_mode_info_valid(&edid, lfb);