Kconfig: Add choice of framebuffer mode
Rename `FRAMEBUFFER_KEEP_VESA_MODE` to `LINEAR_FRAMEBUFFER` and put it together with new `VGA_TEXT_FRAMEBUFFER` into a choice. There are two versions of `LINEAR_FRAMEBUFFER` that differ only in the prompt and help text (one for `HAVE_VBE_LINEAR_FRAMEBUFFER` and one for `HAVE_LINEAR_FRAMEBUFFER`). Due to `kconfig_lint` we have to model that with additional symbols. Change-Id: I9144351491a14d9bb5e650c14933b646bc83fab0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/19804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
parent
49d99fcebc
commit
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@ -2,5 +2,5 @@ CONFIG_COLLECT_TIMESTAMPS=y
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# CONFIG_POST_IO is not set
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# CONFIG_POST_DEVICE is not set
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CONFIG_CONSOLE_POST=y
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CONFIG_FRAMEBUFFER_KEEP_VESA_MODE=y
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CONFIG_LINEAR_FRAMEBUFFER=y
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# CONFIG_CONSOLE_SERIAL is not set
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@ -54,7 +54,7 @@ config SEABIOS_THREAD_OPTIONROMS
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config SEABIOS_VGA_COREBOOT
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prompt "Include generated option rom that implements legacy VGA BIOS compatibility"
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default y if !VENDOR_EMULATION
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depends on !VGA_BIOS && MAINBOARD_DO_NATIVE_VGA_INIT
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depends on !(VGA_BIOS || VGA_ROM_RUN) && (VGA_TEXT_FRAMEBUFFER || LINEAR_FRAMEBUFFER)
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bool
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help
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Coreboot can initialize the GPU of some mainboards.
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@ -63,7 +63,7 @@ config MAINBOARD_USE_LIBGFXINIT
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select HAVE_VGA_TEXT_FRAMEBUFFER
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select HAVE_LINEAR_FRAMEBUFFER
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select RAMSTAGE_LIBHWBASE
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select VGA if !FRAMEBUFFER_KEEP_VESA_MODE
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select VGA if VGA_TEXT_FRAMEBUFFER
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select NO_EDID_FILL_FB
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default n
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help
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@ -539,16 +539,44 @@ config FRAMEBUFFER_VESA_MODE
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default 0x11B if FRAMEBUFFER_VESA_MODE_11B
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default 0x117 if FRAMEBUFFER_VESA_MODE_USER
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config FRAMEBUFFER_KEEP_VESA_MODE
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prompt "Keep VESA framebuffer"
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bool
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depends on HAVE_VGA_TEXT_FRAMEBUFFER && (HAVE_VBE_LINEAR_FRAMEBUFFER || HAVE_LINEAR_FRAMEBUFFER)
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choice
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prompt "Framebuffer mode"
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default VGA_TEXT_FRAMEBUFFER
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config VGA_TEXT_FRAMEBUFFER
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bool "Legacy VGA text mode"
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depends on HAVE_VGA_TEXT_FRAMEBUFFER
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help
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If this option is enabled, coreboot will initialize graphics in
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legacy VGA text mode or, if a VGA BIOS is used and a VESA mode set,
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switch to text mode before handing control to a payload.
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config VBE_LINEAR_FRAMEBUFFER
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bool "VESA framebuffer"
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depends on HAVE_VBE_LINEAR_FRAMEBUFFER
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help
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This option keeps the framebuffer mode set after coreboot finishes
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execution. If this option is enabled, coreboot will pass a
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framebuffer entry in its coreboot table and the payload will need a
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framebuffer driver. If this option is disabled, coreboot will switch
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back to text mode before handing control to a payload.
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compatible driver.
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config GENERIC_LINEAR_FRAMEBUFFER
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bool "Linear \"high-resolution\" framebuffer"
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depends on HAVE_LINEAR_FRAMEBUFFER
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help
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This option enables a high-resolution, linear framebuffer. If this
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option is enabled, coreboot will pass a framebuffer entry in its
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coreboot table and the payload will need a compatible driver.
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endchoice
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# Workaround to have LINEAR_FRAMEBUFFER set in both cases
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# VBE_LINEAR_FRAMEBUFFER and GENERIC_LINEAR_FRAMEBUFFER.
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# `kconfig_lint` doesn't let us use the same name with
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# different texts in the choice above.
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config LINEAR_FRAMEBUFFER
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def_bool y
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depends on VBE_LINEAR_FRAMEBUFFER || GENERIC_LINEAR_FRAMEBUFFER
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config BOOTSPLASH
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prompt "Show graphical bootsplash"
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@ -16,11 +16,11 @@ config DRIVERS_EMULATION_QEMU_BOCHS
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config DRIVERS_EMULATION_QEMU_BOCHS_XRES
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int "bochs vga xres"
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default 800
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depends on FRAMEBUFFER_KEEP_VESA_MODE
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depends on LINEAR_FRAMEBUFFER
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depends on DRIVERS_EMULATION_QEMU_BOCHS
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config DRIVERS_EMULATION_QEMU_BOCHS_YRES
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int "bochs vga yres"
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default 600
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depends on FRAMEBUFFER_KEEP_VESA_MODE
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depends on LINEAR_FRAMEBUFFER
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depends on DRIVERS_EMULATION_QEMU_BOCHS
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@ -41,7 +41,6 @@
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#define VBE_DISPI_LFB_ENABLED 0x40
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#define VBE_DISPI_NOCLEARMEM 0x80
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#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
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static int width = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_XRES;
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static int height = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_YRES;
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@ -56,11 +55,9 @@ static int bochs_read(int index)
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outw(index, VBE_DISPI_IOPORT_INDEX);
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return inw(VBE_DISPI_IOPORT_DATA);
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}
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#endif
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static void bochs_init(struct device *dev)
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static void bochs_init_linear_fb(struct device *dev)
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{
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#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
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struct edid edid;
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int id, mem, bar;
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u32 addr;
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@ -115,10 +112,20 @@ static void bochs_init(struct device *dev)
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edid.panel_bits_per_pixel = 24;
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edid_set_framebuffer_bits_per_pixel(&edid, 32, 0);
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set_vbe_mode_info_valid(&edid, addr);
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#else
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}
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static void bochs_init_text_mode(struct device *dev)
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{
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vga_misc_write(0x1);
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vga_textmode_init();
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#endif
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}
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static void bochs_init(struct device *dev)
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{
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if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER))
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bochs_init_linear_fb(dev);
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else if (IS_ENABLED(CONFIG_VGA_TEXT_FRAMEBUFFER))
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bochs_init_text_mode(dev);
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}
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static struct device_operations qemu_graph_ops = {
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@ -31,11 +31,9 @@
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#include <pc80/vga.h>
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#include <pc80/vga_io.h>
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#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
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static int width = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_XRES;
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static int height = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_YRES;
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static u32 addr = 0;
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#endif
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enum
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{
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@ -194,7 +192,6 @@ enum
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#define CIRRUS_SR_EXTENDED_MODE_32BPP 0x08
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#define CIRRUS_HIDDEN_DAC_888COLOR 0xc5
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#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
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static void
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write_hidden_dac (uint8_t data)
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{
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@ -205,11 +202,9 @@ write_hidden_dac (uint8_t data)
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inb (0x3c6);
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outb (data, 0x3c6);
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}
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#endif
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static void cirrus_init(struct device *dev)
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static void cirrus_init_linear_fb(struct device *dev)
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{
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#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
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uint8_t cr_ext, cr_overlay;
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unsigned pitch = (width * 4) / VGA_CR_PITCH_DIVISOR;
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uint8_t sr_ext = 0, hidden_dac = 0;
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@ -334,11 +329,20 @@ static void cirrus_init(struct device *dev)
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edid.panel_bits_per_pixel = 24;
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edid_set_framebuffer_bits_per_pixel(&edid, 32, 0);
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set_vbe_mode_info_valid(&edid, addr);
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#else
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vga_misc_write(0x1);
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}
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static void cirrus_init_text_mode(struct device *dev)
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{
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vga_misc_write(0x1);
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vga_textmode_init();
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#endif
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}
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static void cirrus_init(struct device *dev)
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{
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if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER))
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cirrus_init_linear_fb(dev);
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else if (IS_ENABLED(CONFIG_VGA_TEXT_FRAMEBUFFER))
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cirrus_init_text_mode(dev);
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}
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static struct device_operations qemu_cirrus_graph_ops = {
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@ -39,7 +39,7 @@ CONFIG_GFX_GMA_DEFAULT_MMIO := 0 # dummy, will be overwritten at runtime
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subdirs-y += ../../../../3rdparty/libgfxinit
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ramstage-y += gma.ads
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ifeq ($(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE),y)
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ifeq ($(CONFIG_LINEAR_FRAMEBUFFER),y)
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ramstage-y += hires_fb/gma.adb
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else
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ramstage-y += text_fb/gma.adb
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@ -6,11 +6,13 @@ void __attribute__((weak)) set_boot_successful(void) { }
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void boot_successful(void)
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{
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#if CONFIG_FRAMEBUFFER_SET_VESA_MODE && !CONFIG_FRAMEBUFFER_KEEP_VESA_MODE
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void vbe_textmode_console(void);
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if (IS_ENABLED(CONFIG_FRAMEBUFFER_SET_VESA_MODE) &&
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IS_ENABLED(CONFIG_VGA_TEXT_FRAMEBUFFER)) {
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void vbe_textmode_console(void);
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vbe_textmode_console();
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}
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vbe_textmode_console();
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#endif
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/* Remember this was a successful boot */
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set_boot_successful();
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@ -109,7 +109,7 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info,
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hfront_porch = mode->hso;
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vfront_porch = mode->vso;
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if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
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if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
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vga_sr_write(1, 1);
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vga_sr_write(0x2, 0xf);
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vga_sr_write(0x3, 0x0);
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@ -263,7 +263,7 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info,
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write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
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write32(mmio + PF_WIN_POS(0), 0);
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if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
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if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
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write32(mmio + PIPESRC(0), ((hactive - 1) << 16)
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| (vactive - 1));
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write32(mmio + PF_CTL(0), 0);
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@ -281,7 +281,7 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info,
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write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
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write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
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if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
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if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
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write32(mmio + VGACNTRL, VGA_DISP_DISABLE);
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write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE
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| DISPPLANE_BGRX888);
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@ -307,7 +307,7 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info,
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write32(mmio + DEIIR, 0xffffffff);
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write32(mmio + SDEIIR, 0xffffffff);
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if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
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if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
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memset((void *) lfb, 0,
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edid->x_resolution * edid->y_resolution * 4);
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set_vbe_mode_info_valid(edid, lfb);
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@ -390,7 +390,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info,
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vfront_porch = mode->vso;
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target_frequency = mode->pixel_clock;
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if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
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if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
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vga_sr_write(1, 1);
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vga_sr_write(0x2, 0xf);
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vga_sr_write(0x3, 0x0);
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@ -520,7 +520,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info,
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write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
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write32(mmio + PF_WIN_POS(0), 0);
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if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
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if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
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write32(mmio + PIPESRC(0), ((hactive - 1) << 16)
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| (vactive - 1));
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write32(mmio + PF_CTL(0), 0);
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@ -539,7 +539,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info,
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write32(mmio + PIPECONF(0), PIPECONF_ENABLE
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| PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
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if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
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if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
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write32(mmio + VGACNTRL, VGA_DISP_DISABLE);
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write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE
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| DISPPLANE_BGRX888);
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@ -569,7 +569,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info,
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write32(mmio + DEIIR, 0xffffffff);
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write32(mmio + SDEIIR, 0xffffffff);
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if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
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if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
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memset((void *) lfb, 0,
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edid->x_resolution * edid->y_resolution * 4);
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set_vbe_mode_info_valid(edid, lfb);
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@ -217,7 +217,7 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf,
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BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) /
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(pixel_n + 2) / (pixel_p1 * pixel_p2));
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if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
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if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
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/* Disable panel fitter (we're in native resolution). */
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write32(mmiobase + PF_CTL(0), 0);
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write32(mmiobase + PF_WIN_SZ(0), 0);
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@ -280,7 +280,7 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf,
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((vactive + bottom_border + vfront_porch + vsync - 1) << 16)
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| (vactive + bottom_border + vfront_porch - 1));
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if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
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if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
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write32(mmiobase + PIPESRC(1), ((hactive - 1) << 16)
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| (vactive - 1));
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} else {
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@ -359,7 +359,7 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf,
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else
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printk(BIOS_ERR, "ERROR: GTT is still Disabled!!!\n");
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if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
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if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
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printk(BIOS_SPEW, "memset %p to 0x00 for %d bytes\n",
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(void *)pgfx, hactive * vactive * 4);
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memset((void *)pgfx, 0x00, hactive * vactive * 4);
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@ -724,32 +724,33 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
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target_frequency = mode->lvds_dual_channel ? mode->pixel_clock
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: (2 * mode->pixel_clock);
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vga_textmode_init();
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#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
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vga_sr_write(1, 1);
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vga_sr_write(0x2, 0xf);
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vga_sr_write(0x3, 0x0);
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vga_sr_write(0x4, 0xe);
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vga_gr_write(0, 0x0);
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vga_gr_write(1, 0x0);
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vga_gr_write(2, 0x0);
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vga_gr_write(3, 0x0);
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vga_gr_write(4, 0x0);
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vga_gr_write(5, 0x0);
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vga_gr_write(6, 0x5);
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vga_gr_write(7, 0xf);
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vga_gr_write(0x10, 0x1);
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vga_gr_write(0x11, 0);
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if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
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vga_sr_write(1, 1);
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vga_sr_write(0x2, 0xf);
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vga_sr_write(0x3, 0x0);
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vga_sr_write(0x4, 0xe);
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vga_gr_write(0, 0x0);
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vga_gr_write(1, 0x0);
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vga_gr_write(2, 0x0);
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vga_gr_write(3, 0x0);
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vga_gr_write(4, 0x0);
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vga_gr_write(5, 0x0);
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vga_gr_write(6, 0x5);
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vga_gr_write(7, 0xf);
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vga_gr_write(0x10, 0x1);
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vga_gr_write(0x11, 0);
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edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;
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edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;
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write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888);
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write32(mmio + DSPADDR(0), 0);
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write32(mmio + DSPSTRIDE(0), edid.bytes_per_line);
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write32(mmio + DSPSURF(0), 0);
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for (i = 0; i < 0x100; i++)
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write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);
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#endif
|
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write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888);
|
||||
write32(mmio + DSPADDR(0), 0);
|
||||
write32(mmio + DSPSTRIDE(0), edid.bytes_per_line);
|
||||
write32(mmio + DSPSURF(0), 0);
|
||||
for (i = 0; i < 0x100; i++)
|
||||
write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);
|
||||
}
|
||||
|
||||
/* Find suitable divisors. */
|
||||
for (candp1 = 1; candp1 <= 8; candp1++) {
|
||||
|
@ -883,15 +884,15 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
|
|||
write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
|
||||
|
||||
write32(mmio + PF_WIN_POS(0), 0);
|
||||
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
|
||||
write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1));
|
||||
write32(mmio + PF_CTL(0),0);
|
||||
write32(mmio + PF_WIN_SZ(0), 0);
|
||||
#else
|
||||
write32(mmio + PIPESRC(0), (639 << 16) | 399);
|
||||
write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
|
||||
write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
|
||||
#endif
|
||||
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
|
||||
write32(mmio + PIPESRC(0), (hactive - 1) << 16 | (vactive - 1));
|
||||
write32(mmio + PF_CTL(0), 0);
|
||||
write32(mmio + PF_WIN_SZ(0), 0);
|
||||
} else {
|
||||
write32(mmio + PIPESRC(0), (639 << 16) | 399);
|
||||
write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3);
|
||||
write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
|
||||
}
|
||||
|
||||
mdelay(1);
|
||||
|
||||
|
@ -911,17 +912,18 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
|
|||
write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
|
||||
write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
|
||||
|
||||
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
|
||||
write32(mmio + CPU_VGACNTRL, 0x20298e | VGA_DISP_DISABLE);
|
||||
#else
|
||||
write32(mmio + CPU_VGACNTRL, 0x20298e);
|
||||
#endif
|
||||
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER))
|
||||
write32(mmio + CPU_VGACNTRL, 0x20298e | VGA_DISP_DISABLE);
|
||||
else
|
||||
write32(mmio + CPU_VGACNTRL, 0x20298e);
|
||||
|
||||
train_link(mmio);
|
||||
|
||||
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
|
||||
write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
|
||||
mdelay(1);
|
||||
#endif
|
||||
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
|
||||
write32(mmio + DSPCNTR(0),
|
||||
DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
|
||||
mdelay(1);
|
||||
}
|
||||
|
||||
write32(mmio + TRANS_HTOTAL(0),
|
||||
((hactive + right_border + hblank - 1) << 16)
|
||||
|
@ -946,11 +948,8 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
|
|||
write32(mmio + 0x00060100, 0xb01c4000);
|
||||
write32(mmio + 0x000f000c, 0xb01a2050);
|
||||
mdelay(1);
|
||||
write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC
|
||||
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
|
||||
| TRANS_STATE_MASK
|
||||
#endif
|
||||
);
|
||||
write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC |
|
||||
(IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER) ? TRANS_STATE_MASK : 0));
|
||||
write32(mmio + PCH_LVDS,
|
||||
LVDS_PORT_ENABLE
|
||||
| (hpolarity << 20) | (vpolarity << 21)
|
||||
|
@ -988,10 +987,11 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
|
|||
write32(mmio + 0x0004f04c, 0x7f7f0000);
|
||||
write32(mmio + 0x0004f054, 0x0000020d);
|
||||
|
||||
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
|
||||
memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4);
|
||||
set_vbe_mode_info_valid(&edid, lfb);
|
||||
#endif
|
||||
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
|
||||
memset((void *)lfb, 0,
|
||||
edid.x_resolution * edid.y_resolution * 4);
|
||||
set_vbe_mode_info_valid(&edid, lfb);
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
@ -217,7 +217,7 @@ int i915lightup_ivy(const struct i915_gpu_controller_info *info,
|
|||
u32 pixel_m2 = 1;
|
||||
|
||||
vga_textmode_init();
|
||||
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
|
||||
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
|
||||
vga_sr_write(1, 1);
|
||||
vga_sr_write(0x2, 0xf);
|
||||
vga_sr_write(0x3, 0x0);
|
||||
|
@ -387,7 +387,7 @@ int i915lightup_ivy(const struct i915_gpu_controller_info *info,
|
|||
|
||||
write32(mmio + 0xf0008, 0);
|
||||
|
||||
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
|
||||
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
|
||||
write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1));
|
||||
write32(mmio + PF_CTL(0),0);
|
||||
write32(mmio + PF_WIN_SZ(0), 0);
|
||||
|
@ -408,7 +408,7 @@ int i915lightup_ivy(const struct i915_gpu_controller_info *info,
|
|||
|
||||
link_train(mmio);
|
||||
|
||||
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE))
|
||||
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER))
|
||||
write32(mmio+CPU_VGACNTRL,0x298e | VGA_DISP_DISABLE);
|
||||
else
|
||||
write32(mmio+CPU_VGACNTRL,0x298e);
|
||||
|
@ -419,7 +419,7 @@ int i915lightup_ivy(const struct i915_gpu_controller_info *info,
|
|||
mdelay(1);
|
||||
read32(mmio + 0x000f0014); // = 0x00000600
|
||||
|
||||
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
|
||||
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
|
||||
write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE
|
||||
| DISPPLANE_BGRX888);
|
||||
mdelay(1);
|
||||
|
@ -451,7 +451,7 @@ int i915lightup_ivy(const struct i915_gpu_controller_info *info,
|
|||
|
||||
mdelay(1);
|
||||
|
||||
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE))
|
||||
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER))
|
||||
write32(mmio + PCH_TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC
|
||||
| TRANS_STATE_MASK);
|
||||
else
|
||||
|
@ -490,7 +490,7 @@ int i915lightup_ivy(const struct i915_gpu_controller_info *info,
|
|||
write32(mmio + DEIIR, 0xffffffff);
|
||||
write32(mmio + SDEIIR, 0xffffffff);
|
||||
|
||||
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
|
||||
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
|
||||
memset ((void *) lfb, 0, edid.x_resolution
|
||||
* edid.y_resolution * 4);
|
||||
set_vbe_mode_info_valid(&edid, lfb);
|
||||
|
|
|
@ -200,7 +200,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
|
|||
target_frequency = mode->lvds_dual_channel ? mode->pixel_clock
|
||||
: (2 * mode->pixel_clock);
|
||||
|
||||
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
|
||||
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
|
||||
vga_sr_write(1, 1);
|
||||
vga_sr_write(0x2, 0xf);
|
||||
vga_sr_write(0x3, 0x0);
|
||||
|
@ -361,7 +361,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
|
|||
write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
|
||||
|
||||
write32(mmio + PF_WIN_POS(0), 0);
|
||||
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
|
||||
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
|
||||
write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1));
|
||||
write32(mmio + PF_CTL(0),0);
|
||||
write32(mmio + PF_WIN_SZ(0), 0);
|
||||
|
@ -388,14 +388,14 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
|
|||
write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
|
||||
write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
|
||||
|
||||
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE))
|
||||
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER))
|
||||
write32(mmio + CPU_VGACNTRL, 0x20298e | VGA_DISP_DISABLE);
|
||||
else
|
||||
write32(mmio + CPU_VGACNTRL, 0x20298e);
|
||||
|
||||
train_link(mmio);
|
||||
|
||||
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
|
||||
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
|
||||
write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
|
||||
mdelay(1);
|
||||
}
|
||||
|
@ -424,7 +424,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
|
|||
write32(mmio + 0x000f000c, 0x801a2350);
|
||||
mdelay(1);
|
||||
|
||||
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE))
|
||||
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER))
|
||||
write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC
|
||||
| TRANS_STATE_MASK);
|
||||
else
|
||||
|
@ -462,7 +462,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
|
|||
write32(mmio + DEIIR, 0xffffffff);
|
||||
write32(mmio + SDEIIR, 0xffffffff);
|
||||
|
||||
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
|
||||
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
|
||||
memset ((void *) lfb, 0, edid.x_resolution
|
||||
* edid.y_resolution * 4);
|
||||
set_vbe_mode_info_valid(&edid, lfb);
|
||||
|
|
|
@ -143,7 +143,7 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info,
|
|||
} else
|
||||
printk(BIOS_DEBUG, "EDID is null, using 640 x 480 @ 60Hz mode");
|
||||
|
||||
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
|
||||
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
|
||||
vga_sr_write(1, 1);
|
||||
vga_sr_write(0x2, 0xf);
|
||||
vga_sr_write(0x3, 0x0);
|
||||
|
@ -274,7 +274,7 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info,
|
|||
write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
|
||||
|
||||
write32(mmio + PF_WIN_POS(0), 0);
|
||||
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
|
||||
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
|
||||
write32(mmio + PIPESRC(0), ((hactive - 1) << 16)
|
||||
| (vactive - 1));
|
||||
write32(mmio + PF_CTL(0), 0);
|
||||
|
@ -293,7 +293,7 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info,
|
|||
write32(mmio + PIPECONF(0), PIPECONF_ENABLE
|
||||
| PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
|
||||
|
||||
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
|
||||
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
|
||||
write32(mmio + VGACNTRL, VGA_DISP_DISABLE);
|
||||
write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE
|
||||
| DISPPLANE_BGRX888);
|
||||
|
@ -323,7 +323,7 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info,
|
|||
write32(mmio + DEIIR, 0xffffffff);
|
||||
write32(mmio + SDEIIR, 0xffffffff);
|
||||
|
||||
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
|
||||
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
|
||||
memset((void *) lfb, 0,
|
||||
hactive * vactive * 4);
|
||||
set_vbe_mode_info_valid(&edid, lfb);
|
||||
|
|
Loading…
Reference in New Issue