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mb/google/dedede: Update the SLP_Sx assertion widths and PwrCycDur 

This patch updates the SLP_Sx assertion width and power cycle duration
for the dedede platforms.

Power cycle duration:
With default value,
	S0->S5 -> [ ~4.2 seconds delay ] -> S5->S0

With value set to 1,
	S0->S5 -> [ ~1.2 seconds delay ] -> S5->S0

BUG=b:159104150
TEST=Verified that the power cycle duration is ~1.2s with global
     reset on waddledoo.

Change-Id: I7079cbd564288b5d5b69e07661434439365063d3
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This commit is contained in:
V Sowmya 2020-07-24 09:16:05 +05:30 committed by Subrata Banik
parent 7aee5c67a1
commit 6d92ab8932
1 changed files with 14 additions and 0 deletions
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14
src/mainboard/google/dedede/variants/baseboard/devicetree.cb
View File

@ -166,6 +166,20 @@ chip soc/intel/jasperlake
# Skip the CPU repalcement check # Skip the CPU repalcement check
register "SkipCpuReplacementCheck" = "1" register "SkipCpuReplacementCheck" = "1"
# Set the minimum assertion width
register "PchPmSlpS3MinAssert" = "3" # 50ms
register "PchPmSlpS4MinAssert" = "1" # 1s
register "PchPmSlpSusMinAssert" = "3" # 1s
register "PchPmSlpAMinAssert" = "3" # 98ms
# NOTE: Duration programmed in the below register should never be smaller than the
# stretch duration programmed in the following registers -
# - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert)
# - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert)
# - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert)
# - PM_CFG.SLP_LAN_MIN_ASST_WDTH
register "PchPmPwrCycDur" = "1" # 1s
device domain 0 on device domain 0 on
device pci 00.0 on end # Host Bridge device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device device pci 02.0 on end # Integrated Graphics Device