GNUBoot/coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

mb/google/guybrush: Populate PIC IRQ data

Browse source 
The PIC IRQs are required so we can correctly set up the PCI_INT
registers. This only matters when booting in PIC mode. We don't need to
set the IO-APIC registers since the linux kernel will auto-assign those
to reduce conflicts.

BUG=b:184766519
TEST=Boot guybrush with `pci=nomsi,noacpi amd_iommu=off noapic` and
verify xhci and graphics continue to work.

$ cat /proc/interrupts
 12:     285064      XT-PIC      nvme0q0, nvme0q1, rtw88_pci
 13:     100000      XT-PIC      xhci-hcd:usb1
 14:       4032      XT-PIC      amdgpu, xhci-hcd:usb3

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1d66ccd08a86a64242dbc909c57ff9685828f61f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52915
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Raul E Rangel 2021-05-04 14:29:09 -06:00 committed by Felix Held
parent f486fcc998
commit 6d9a0eab70
1 changed files with 8 additions and 8 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

16
src/mainboard/google/guybrush/mainboard.c
View file

@ -47,14 +47,14 @@ static const struct fch_irq_routing {
uint8_t pic_irq_num;
uint8_t apic_irq_num;
} guybrush_fch[] = {
{ PIRQ_A, PIRQ_NC, PIRQ_NC },
{ PIRQ_B, PIRQ_NC, PIRQ_NC },
{ PIRQ_C, PIRQ_NC, PIRQ_NC },
{ PIRQ_D, PIRQ_NC, PIRQ_NC },
{ PIRQ_E, PIRQ_NC, PIRQ_NC },
{ PIRQ_F, PIRQ_NC, PIRQ_NC },
{ PIRQ_G, PIRQ_NC, PIRQ_NC },
{ PIRQ_H, PIRQ_NC, PIRQ_NC },
{ PIRQ_A, 12, PIRQ_NC },
{ PIRQ_B, 14, PIRQ_NC },
{ PIRQ_C, 15, PIRQ_NC },
{ PIRQ_D, 12, PIRQ_NC },
{ PIRQ_E, 14, PIRQ_NC },
{ PIRQ_F, 15, PIRQ_NC },
{ PIRQ_G, 12, PIRQ_NC },
{ PIRQ_H, 14, PIRQ_NC },
{ PIRQ_SCI, ACPI_SCI_IRQ, ACPI_SCI_IRQ },
{ PIRQ_SD, PIRQ_NC, PIRQ_NC },