GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

EXYNOS5250: be less chatty at critical moments 

The 5250 DRAM code is *really* chatty. That's not a great
idea in time critical code, and DRAM init is generally
very sensitive about such things.

Finally, for those things that are errors, print them
at an error level, not a debug level.

Change-Id: Ifa86b019dfd5f8ae6c8a1da2a35b5d0808dc3623
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/60100
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-on: http://review.coreboot.org/4359
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Ronald G. Minnich 2013-06-26 09:51:21 -07:00 committed by Stefan Reinauer
parent 3641cb1d66
commit 6da7046f73
1 changed files with 5 additions and 31 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
src/cpu/samsung/exynos5250/dmc_init_ddr3.c
View File

@ -65,41 +65,30 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
phy1_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY1_BASE;
dmc = (struct exynos5_dmc *)EXYNOS5_DMC_CTRL_BASE;
if (mem_reset) {
printk(BIOS_SPEW, "%s: reset phy: ", __func__);
if (mem_reset)
reset_phy_ctrl();
printk(BIOS_SPEW, "done\n");
} else {
printk(BIOS_SPEW, "%s: skip mem_reset.\n", __func__);
}
/* Set Impedance Output Driver */
printk(BIOS_SPEW, "ddr3_mem_ctrl_init: Set Impedance Output Driver\n");
printk(BIOS_SPEW, "ddr3_mem_ctrl_init: mem->impedance 0x%x\n",
mem->impedance);
val = (mem->impedance << CA_CK_DRVR_DS_OFFSET) |
(mem->impedance << CA_CKE_DRVR_DS_OFFSET) |
(mem->impedance << CA_CS_DRVR_DS_OFFSET) |
(mem->impedance << CA_ADR_DRVR_DS_OFFSET);
printk(BIOS_SPEW, "ddr3_mem_ctrl_init: val 0x%x\n", val);
writel(val, &phy0_ctrl->phy_con39);
writel(val, &phy1_ctrl->phy_con39);
/* Set Read Latency and Burst Length for PHY0 and PHY1 */
printk(BIOS_SPEW, "ddr3_mem_ctrl_init: "
"Set Read Latency and Burst Length for PHY0 and PHY1\n");
val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) |
(mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT);
writel(val, &phy0_ctrl->phy_con42);
writel(val, &phy1_ctrl->phy_con42);
/* ZQ Calibration */
printk(BIOS_SPEW, "ddr3_mem_ctrl_init: ZQ Calibration\n");
if (dmc_config_zq(mem, phy0_ctrl, phy1_ctrl))
if (dmc_config_zq(mem, phy0_ctrl, phy1_ctrl)) {
printk(BIOS_EMERG, "DRAM ZQ CALIBRATION FAILURE\n");
return SETUP_ERR_ZQ_CALIBRATION_FAILURE;
}
/* DQ Signal */
printk(BIOS_SPEW, "ddr3_mem_ctrl_init: DQ Signal\n");
writel(mem->phy0_pulld_dqs, &phy0_ctrl->phy_con14);
writel(mem->phy1_pulld_dqs, &phy1_ctrl->phy_con14);
@ -110,7 +99,6 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
update_reset_dll(dmc, DDR_MODE_DDR3);
/* DQS Signal */
printk(BIOS_SPEW, "ddr3_mem_ctrl_init: DQS Signal\n");
writel(mem->phy0_dqs, &phy0_ctrl->phy_con4);
writel(mem->phy1_dqs, &phy1_ctrl->phy_con4);
@ -128,7 +116,6 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
writel(val, &phy1_ctrl->phy_con12);
/* Start DLL locking */
printk(BIOS_SPEW, "ddr3_mem_ctrl_init: Start DLL Locking\n");
writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
&phy0_ctrl->phy_con12);
writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
@ -140,12 +127,9 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
&dmc->concontrol);
/* Memory Channel Interleaving Size */
printk(BIOS_SPEW, "ddr3_mem_ctrl_init: "
"Memory Channel Interleaving Size\n");
writel(mem->iv_size, &dmc->ivcontrol);
/* Set DMC MEMCONTROL register */
printk(BIOS_SPEW, "ddr3_mem_ctrl_init: Set DMC MEMCONTROL register\n");
val = mem->memcontrol & ~DMC_MEMCONTROL_DSREF_ENABLE;
writel(val, &dmc->memcontrol);
@ -155,13 +139,10 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
writel(mem->membaseconfig1, &dmc->membaseconfig1);
/* Precharge Configuration */
printk(BIOS_SPEW, "ddr3_mem_ctrl_init: Precharge Configuration\n");
writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
&dmc->prechconfig);
/* Power Down mode Configuration */
printk(BIOS_SPEW, "ddr3_mem_ctrl_init: "
"Power Down mode Configuration\n");
writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT |
mem->dsref_cyc << PWRDNCONFIG_DSREF_CYC_SHIFT,
&dmc->pwrdnconfig);
@ -169,19 +150,15 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
/* TimingRow, TimingData, TimingPower and Timingaref
* values as per Memory AC parameters
*/
printk(BIOS_SPEW, "ddr3_mem_ctrl_init: "
"TimingRow, TimingData, TimingPower and Timingaref\n");
writel(mem->timing_ref, &dmc->timingref);
writel(mem->timing_row, &dmc->timingrow);
writel(mem->timing_data, &dmc->timingdata);
writel(mem->timing_power, &dmc->timingpower);
/* Send PALL command */
printk(BIOS_SPEW, "ddr3_mem_ctrl_init: Send PALL Command\n");
dmc_config_prech(mem, dmc);
/* Send NOP, MRS and ZQINIT commands */
printk(BIOS_SPEW, "ddr3_mem_ctrl_init: Send NOP, MRS, and ZQINIT\n");
dmc_config_mrs(mem, dmc);
if (mem->gate_leveling_enable) {
@ -241,7 +218,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
i--;
}
if (!i){
printk(BIOS_SPEW, "Timeout on RDLVL. No DRAM.\n");
printk(BIOS_EMERG, "Timeout on RDLVL. No DRAM.\n");
return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
}
writel(CTRL_RDLVL_GATE_DISABLE, &dmc->rdlvl_config);
@ -263,14 +240,11 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
}
/* Send PALL command */
printk(BIOS_SPEW, "ddr3_mem_ctrl_init: Send PALL Command\n");
dmc_config_prech(mem, dmc);
writel(mem->memcontrol, &dmc->memcontrol);
/* Set DMC Concontrol and enable auto-refresh counter */
printk(BIOS_SPEW, "ddr3_mem_ctrl_init: "
"Set DMC Concontrol and enable auto-refresh counter\n");
writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)
| (mem->aref_en << CONCONTROL_AREF_EN_SHIFT), &dmc->concontrol);
return 0;