mainboard/sunw/ultra40/romstage.c: Use tabs for indents
Change-Id: I9b7be74625dfcb6317a1cdb61d0dc77d7f359462 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16776 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Elyes HAOUAS
Martin Roth
parent
8f372d031b
commit
6da74da345
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@ -30,12 +30,12 @@ static void memreset(int controllers, const struct mem_controller *ctrl) { }
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#ifdef ENABLE_ONBOARD_SCSI
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static void sio_gpio_setup(void)
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{
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unsigned value;
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unsigned value;
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/*Enable onboard scsi*/
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lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1 << 7)|(0 << 2)|(0 << 1)|(0 << 0)); // GP21, offset 0x2c, DISABLE_SCSI_L
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value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
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lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1 << 1)));
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/*Enable onboard scsi*/
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lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1 << 7)|(0 << 2)|(0 << 1)|(0 << 0)); // GP21, offset 0x2c, DISABLE_SCSI_L
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value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
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lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1 << 1)));
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}
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#endif
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@ -55,12 +55,12 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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//set GPIO to input mode
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#define CK804_MB_SETUP \
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RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/ \
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RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
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RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
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RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/ \
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RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
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RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
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RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/ \
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RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
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RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
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RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/ \
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RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
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RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
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#include "southbridge/nvidia/ck804/early_setup_car.c"
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#include "cpu/amd/model_fxx/init_cpus.c"
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@ -68,25 +68,25 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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static void sio_setup(void)
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{
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unsigned value;
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uint32_t dword;
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uint8_t byte;
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unsigned value;
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uint32_t dword;
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uint8_t byte;
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pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
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pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
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byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
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byte |= 0x20;
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pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
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byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
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byte |= 0x20;
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pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
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dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
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dword |= (1 << 29)|(1 << 0);
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pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
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dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
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dword |= (1 << 29)|(1 << 0);
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pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
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lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
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lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
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value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
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value &= 0xbf;
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lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
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value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
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value &= 0xbf;
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lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
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}
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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@ -100,49 +100,49 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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DIMM5, DIMM7, 0, 0,
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};
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int needs_reset;
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unsigned bsp_apicid = 0, nodes;
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struct mem_controller ctrl[8];
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int needs_reset;
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unsigned bsp_apicid = 0, nodes;
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struct mem_controller ctrl[8];
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if (!cpu_init_detectedx && boot_cpu()) {
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if (!cpu_init_detectedx && boot_cpu()) {
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/* Nothing special needs to be done to find bus 0 */
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/* Allow the HT devices to be found */
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enumerate_ht_chain();
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sio_setup();
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}
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}
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if (bist == 0)
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bsp_apicid = init_cpus(cpu_init_detectedx);
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if (bist == 0)
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bsp_apicid = init_cpus(cpu_init_detectedx);
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lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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console_init();
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console_init();
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/* Halt if there was a built in self test failure */
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report_bist_failure(bist);
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setup_ultra40_resource_map();
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setup_ultra40_resource_map();
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needs_reset = setup_coherent_ht_domain();
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wait_all_core0_started();
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wait_all_core0_started();
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#if CONFIG_LOGICAL_CPUS
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// It is said that we should start core1 after all core0 launched
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start_other_cores();
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wait_all_other_cores_started(bsp_apicid);
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// It is said that we should start core1 after all core0 launched
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start_other_cores();
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wait_all_other_cores_started(bsp_apicid);
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#endif
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needs_reset |= ht_setup_chains_x();
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needs_reset |= ck804_early_setup_x();
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if (needs_reset) {
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printk(BIOS_INFO, "ht reset -\n");
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soft_reset();
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}
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needs_reset |= ht_setup_chains_x();
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needs_reset |= ck804_early_setup_x();
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if (needs_reset) {
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printk(BIOS_INFO, "ht reset -\n");
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soft_reset();
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}
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allow_all_aps_stop(bsp_apicid);
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allow_all_aps_stop(bsp_apicid);
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nodes = get_nodes();
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//It's the time to set ctrl now;
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fill_mem_ctrl(nodes, ctrl, spd_addr);
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nodes = get_nodes();
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//It's the time to set ctrl now;
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fill_mem_ctrl(nodes, ctrl, spd_addr);
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enable_smbus();
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