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mb/google/brya/var/kano: Add gpio-keys ACPI node for PENH 

Use gpio_keys driver to add ACPI node for pen eject event.  Also
setting gpio wake pin for wake events.

BUG=b:192415743
TEST=build pass

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ia36119678cfd5c65a62685d3312537d9aa21e83b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This commit is contained in:
David Wu 2021-11-09 12:36:43 +08:00 committed by Paul Fagerburg
parent cfa59206a8
commit 6db243acd0
3 changed files with 21 additions and 0 deletions
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1
src/mainboard/google/brya/Kconfig
View File

@ -14,6 +14,7 @@ config BOARD_GOOGLE_BRYA_COMMON
def_bool y def_bool y
select BOARD_ROMSIZE_KB_32768 select BOARD_ROMSIZE_KB_32768
select DRIVERS_GENERIC_ALC1015 select DRIVERS_GENERIC_ALC1015
select DRIVERS_GENERIC_GPIO_KEYS
select DRIVERS_GENERIC_MAX98357A select DRIVERS_GENERIC_MAX98357A
select DRIVERS_I2C_GENERIC select DRIVERS_I2C_GENERIC
select DRIVERS_I2C_HID select DRIVERS_I2C_HID

4
src/mainboard/google/brya/variants/kano/gpio.c
View File

@ -30,10 +30,14 @@ static const struct pad_config override_gpio_table[] = {
PAD_NC(GPP_D3, NONE), PAD_NC(GPP_D3, NONE),
/* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */ /* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
/* D6 : SRCCLKREQ1# ==> APU_PEN_DETECT_ODL */
PAD_CFG_GPI_GPIO_DRIVER(GPP_D6, NONE, PLTRST),
/* D7 : SRCCLKREQ2# ==> NC */ /* D7 : SRCCLKREQ2# ==> NC */
PAD_NC(GPP_D7, NONE), PAD_NC(GPP_D7, NONE),
/* D8 : SRCCLKREQ3# ==> NC */ /* D8 : SRCCLKREQ3# ==> NC */
PAD_NC(GPP_D8, NONE), PAD_NC(GPP_D8, NONE),
/* D17 : UART1_RXD ==> APU_PEN_DETECT_ODL */
PAD_CFG_GPI_SCI(GPP_D17, NONE, DEEP, EDGE_SINGLE, NONE),
/* D18 : UART1_TXD ==> NC */ /* D18 : UART1_TXD ==> NC */
PAD_NC(GPP_D18, NONE), PAD_NC(GPP_D18, NONE),

16
src/mainboard/google/brya/variants/kano/overridetree.cb
View File

@ -15,6 +15,9 @@ end
chip soc/intel/alderlake chip soc/intel/alderlake
register "SaGv" = "SaGv_Enabled" register "SaGv" = "SaGv_Enabled"
# GPE configuration
register "pmc_gpe0_dw1" = "GPP_D"
# FIVR configurations for kano are disabled since the board doesn't have V1p05 and Vnn # FIVR configurations for kano are disabled since the board doesn't have V1p05 and Vnn
# bypass rails implemented. # bypass rails implemented.
register "ext_fivr_settings" = "{ register "ext_fivr_settings" = "{
@ -223,6 +226,19 @@ chip soc/intel/alderlake
register "hid_desc_reg_offset" = "0x01" register "hid_desc_reg_offset" = "0x01"
device i2c 0x10 on end device i2c 0x10 on end
end end
chip drivers/generic/gpio_keys
register "name" = ""PENH""
# GPP_D6 is the IRQ source, and GPP_D17 is the wake source
register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_D6)"
register "key.wake_gpe" = "GPE0_DW1_17"
register "key.wakeup_route" = "WAKEUP_ROUTE_SCI"
register "key.wakeup_event_action" = "EV_ACT_DEASSERTED"
register "key.dev_name" = ""EJCT""
register "key.linux_code" = "SW_PEN_INSERTED"
register "key.linux_input_type" = "EV_SW"
register "key.label" = ""pen_eject""
device generic 0 on end
end
end end
device ref i2c2 on device ref i2c2 on
chip drivers/i2c/sx9324 chip drivers/i2c/sx9324