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mb/google/brya/variants/gimble: add TcssAuxOri 

Gimble don't have retimer on port0, the port need to be configured for the SOC to handle Aux orientation flipping.
Also add "typec_aux_bias_pads" lets the SoC IOM firmware control the Aux DC bias voltages.

BUG=b:195087071
BRANCH=none
TEST=check both orientation can output display on type-c monitor.

Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I057048c14110bb81bf5b5fd0e3151deb031ca5d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Scott Chao 2021-07-30 17:25:38 +08:00 committed by Paul Fagerburg
parent 2cdcc254c8
commit 6db97a31ef
2 changed files with 4 additions and 0 deletions
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2
src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
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@ -3,6 +3,8 @@ chip soc/intel/alderlake
device lapic 0 on end device lapic 0 on end
end end
register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
# GPE configuration # GPE configuration
register "pmc_gpe0_dw0" = "GPP_A" register "pmc_gpe0_dw0" = "GPP_A"
register "pmc_gpe0_dw1" = "GPP_E" register "pmc_gpe0_dw1" = "GPP_E"

2
src/mainboard/google/brya/variants/gimble/overridetree.cb
View File

@ -20,6 +20,8 @@ fw_config
end end
end end
chip soc/intel/alderlake chip soc/intel/alderlake
register "TcssAuxOri" = "1"
register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2_C2 register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2_C2
register "usb2_ports[3]" = "USB2_PORT_EMPTY" # M.2 WWAN register "usb2_ports[3]" = "USB2_PORT_EMPTY" # M.2 WWAN
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port