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intel/lynxpoint: Allow to always route USB3 ports to XHCI 

This will make USB keyboards connected to USB3 ports work
in libpayload on Beltino.

BUG=chrome-os-partner:23396
BRANCH=none
TEST=Use USB keyboard on Beltino in dev mode screen

Change-Id: I70b03d733bd9e4c8be5673b48bd2196effa8a5e7
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/173640
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
[pm: rebase to master branch of coreboot upstream]
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/6018
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Stefan Reinauer 2013-10-17 17:00:26 -07:00 committed by Patrick Georgi
parent 32d2e2b360
commit 6dbbe2ee96
2 changed files with 9 additions and 0 deletions
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3
src/southbridge/intel/lynxpoint/chip.h
View File

@ -111,6 +111,9 @@ struct southbridge_intel_lynxpoint_config {
* [24] = CLKOUT_ITPXDP * [24] = CLKOUT_ITPXDP
*/ */
uint32_t icc_clock_disable; uint32_t icc_clock_disable;
/* Route USB ports to XHCI per default */
uint8_t xhci_default;
}; };
extern struct chip_operations southbridge_intel_lynxpoint_ops; extern struct chip_operations southbridge_intel_lynxpoint_ops;

6
src/southbridge/intel/lynxpoint/usb_xhci.c
View File

@ -26,6 +26,8 @@
#include <arch/io.h> #include <arch/io.h>
#include "pch.h" #include "pch.h"
typedef struct southbridge_intel_lynxpoint_config config_t;
static u32 usb_xhci_mem_base(device_t dev) static u32 usb_xhci_mem_base(device_t dev)
{ {
u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
@ -294,6 +296,7 @@ static void usb_xhci_init(device_t dev)
u32 reg32; u32 reg32;
u16 reg16; u16 reg16;
u32 mem_base = usb_xhci_mem_base(dev); u32 mem_base = usb_xhci_mem_base(dev);
config_t *config = dev->chip_info;
/* D20:F0:74h[1:0] = 00b (set D0 state) */ /* D20:F0:74h[1:0] = 00b (set D0 state) */
reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS); reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS);
@ -356,6 +359,9 @@ static void usb_xhci_init(device_t dev)
/* Reset ports that are disabled or /* Reset ports that are disabled or
* polling before returning to the OS. */ * polling before returning to the OS. */
usb_xhci_reset_usb3(dev, 0); usb_xhci_reset_usb3(dev, 0);
} else if (config->xhci_default) {
/* Route all ports to XHCI */
outb(0xca, 0xb2);
} }
} }