intel/lynxpoint: Allow to always route USB3 ports to XHCI
This will make USB keyboards connected to USB3 ports work in libpayload on Beltino. BUG=chrome-os-partner:23396 BRANCH=none TEST=Use USB keyboard on Beltino in dev mode screen Change-Id: I70b03d733bd9e4c8be5673b48bd2196effa8a5e7 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://chromium-review.googlesource.com/173640 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> [pm: rebase to master branch of coreboot upstream] Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6018 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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@ -111,6 +111,9 @@ struct southbridge_intel_lynxpoint_config {
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* [24] = CLKOUT_ITPXDP
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*/
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uint32_t icc_clock_disable;
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/* Route USB ports to XHCI per default */
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uint8_t xhci_default;
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};
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extern struct chip_operations southbridge_intel_lynxpoint_ops;
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@ -26,6 +26,8 @@
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#include <arch/io.h>
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#include "pch.h"
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typedef struct southbridge_intel_lynxpoint_config config_t;
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static u32 usb_xhci_mem_base(device_t dev)
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{
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u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
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@ -294,6 +296,7 @@ static void usb_xhci_init(device_t dev)
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u32 reg32;
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u16 reg16;
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u32 mem_base = usb_xhci_mem_base(dev);
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config_t *config = dev->chip_info;
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/* D20:F0:74h[1:0] = 00b (set D0 state) */
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reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS);
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@ -356,6 +359,9 @@ static void usb_xhci_init(device_t dev)
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/* Reset ports that are disabled or
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* polling before returning to the OS. */
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usb_xhci_reset_usb3(dev, 0);
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} else if (config->xhci_default) {
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/* Route all ports to XHCI */
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outb(0xca, 0xb2);
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}
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}
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