config.g change
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1263 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Greg Watson
parent
526fce7f20
commit
6dc0d8c72d
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@ -1,22 +1,31 @@
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uses HAVE_MP_TABLE
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uses HAVE_PIRQ_TABLE
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uses USE_FALLBACK_IMAGE
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uses MAINBOARD
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uses ARCH
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uses USE_OPTION_TABLE
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uses HAVE_FALLBACK_BOOT
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uses HAVE_HARD_RESET
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uses HAVE_OPTION_TABLE
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uses FALLBACK_SIZE
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uses ROM_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_IMAGE_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_SECTION_OFFSET
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uses CONFIG_SMP
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uses CONFIG_MAX_CPUS
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uses CONFIG_IOAPIC
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uses CONFIG_ROM_STREAM
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uses CONFIG_ROM_STREAM_START
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uses PAYLOAD_SIZE
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uses _ROMBASE
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uses XIP_ROM_SIZE
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uses XIP_ROM_BASE
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uses IRQ_SLOT_COUNT
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uses STACK_SIZE
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uses HEAP_SIZE
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## ROM_SIZE is the size of boot ROM that this board will use.
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default ROM_SIZE 524288
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default ROM_SIZE=524288
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###
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### Build options
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@ -25,94 +34,88 @@ default ROM_SIZE 524288
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##
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## Build code for the fallback boot
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##
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option HAVE_FALLBACK_BOOT=1
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default HAVE_FALLBACK_BOOT=1
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##
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## Build code to reset the motherboard from linuxBIOS
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##
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option HAVE_HARD_RESET=1
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default HAVE_HARD_RESET=1
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##
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## Build code to export a programmable irq routing table
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##
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option HAVE_PIRQ_TABLE=1
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option IRQ_SLOT_COUNT=7
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default HAVE_PIRQ_TABLE=1
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default IRQ_SLOT_COUNT=7
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##
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## Build code to export an x86 MP table
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## Useful for specifying IRQ routing values
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##
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option HAVE_MP_TABLE=1
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default HAVE_MP_TABLE=1
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##
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## Build code to export a CMOS option table
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##
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option HAVE_OPTION_TABLE=1
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default HAVE_OPTION_TABLE=1
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##
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## Build code for SMP support
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## Only worry about 2 micro processors
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##
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option CONFIG_SMP=1
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option CONFIG_MAX_CPUS=2
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default CONFIG_SMP=1
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default CONFIG_MAX_CPUS=2
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##
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## Build code to setup a generic IOAPIC
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##
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option CONFIG_IOAPIC=1
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##
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## Clean up the motherboard id strings
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##
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option MAINBOARD_PART_NUMBER="KHEPRI"
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option MAINBOARD_VENDOR="NEWISYS"
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default CONFIG_IOAPIC=1
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###
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### LinuxBIOS layout values
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###
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## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
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option ROM_IMAGE_SIZE = 65536
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default ROM_IMAGE_SIZE = 65536
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##
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## Use a small 8K stack
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##
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option STACK_SIZE=0x2000
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default STACK_SIZE=0x2000
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##
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## Use a small 16K heap
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##
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option HEAP_SIZE=0x4000
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default HEAP_SIZE=0x4000
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##
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## Only use the option table in a normal image
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##
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option USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
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default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
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##
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## Compute the location and size of where this firmware image
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## (linuxBIOS plus bootloader) will live in the boot rom chip.
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##
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if USE_FALLBACK_IMAGE
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option ROM_SECTION_SIZE = FALLBACK_SIZE
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option ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
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default ROM_SECTION_SIZE = FALLBACK_SIZE
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default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
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else
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option ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
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option ROM_SECTION_OFFSET = 0
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default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
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default ROM_SECTION_OFFSET = 0
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end
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##
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## Compute the start location and size size of
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## The linuxBIOS bootloader.
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##
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option PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
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option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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option CONFIG_ROM_STREAM = 1
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default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
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default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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default CONFIG_ROM_STREAM = 1
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##
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## Compute where this copy of linuxBIOS will start in the boot rom
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##
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option _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
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default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
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##
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## Compute a range of ROM that can cached to speed up linuxBIOS,
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@ -121,8 +124,8 @@ option _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
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## XIP_ROM_SIZE must be a power of 2.
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## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
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##
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option XIP_ROM_SIZE=65536
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option XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
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default XIP_ROM_SIZE=65536
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default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
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##
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## Set all of the defaults for an x86 architecture
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