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Use DIMM0 et al in lots more places instead of hardocding values. 

The (0xa << 3) expression equals 0x50, i.e. DIMM0.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6103 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann 2010-11-21 11:36:03 +00:00
parent 86a571797d
commit 6dc92f0d1a
66 changed files with 204 additions and 186 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/amd/db800/romstage.c
View File

@ -65,7 +65,7 @@ void main(unsigned long bist)
post_code(0x01);
static const struct mem_controller memctrl[] = {
{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
{.channel0 = {DIMM0, DIMM1}}
};
SystemPreInit();

2
src/mainboard/amd/norwich/romstage.c
View File

@ -62,7 +62,7 @@ void main(unsigned long bist)
post_code(0x01);
static const struct mem_controller memctrl[] = {
{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
{.channel0 = {DIMM0, DIMM1}}
};
SystemPreInit();

2
src/mainboard/amd/rumba/romstage.c
View File

@ -35,7 +35,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
void main(unsigned long bist)
{
static const struct mem_controller memctrl [] = {
{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
{.channel0 = {DIMM0, DIMM1}}
};
SystemPreInit();

9
src/mainboard/arima/hdama/romstage.c
View File

@ -24,6 +24,7 @@
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include <spd.h>
#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
@ -85,11 +86,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
(0xa<<3)|1, (0xa<<3)|3, 0, 0,
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
(0xa<<3)|4, (0xa<<3)|6, 0, 0,
(0xa<<3)|5, (0xa<<3)|7, 0, 0,
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
#endif
};

2
src/mainboard/artecgroup/dbe61/romstage.c
View File

@ -78,7 +78,7 @@ void main(unsigned long bist)
msr_t msr;
static const struct mem_controller memctrl[] = {
{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
{.channel0 = {DIMM0, DIMM1}}
};
SystemPreInit();

9
src/mainboard/asus/a8n_e/romstage.c
View File

@ -48,6 +48,7 @@
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
static void memreset(int controllers, const struct mem_controller *ctrl)
{
@ -93,11 +94,11 @@ static void sio_setup(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
(0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
(0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
#endif
};

9
src/mainboard/asus/a8v-e_deluxe/romstage.c
View File

@ -46,6 +46,7 @@ unsigned int get_sbdn(unsigned bus);
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include <spd.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED)
@ -154,11 +155,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
// Node 0
(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
// Node 1
(0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
(0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
};
unsigned bsp_apicid = 0;
int needs_reset = 0;

9
src/mainboard/asus/a8v-e_se/romstage.c
View File

@ -46,6 +46,7 @@ unsigned int get_sbdn(unsigned bus);
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include <spd.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED)
@ -154,11 +155,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
// Node 0
(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
// Node 1
(0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
(0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
};
unsigned bsp_apicid = 0;
int needs_reset = 0;

9
src/mainboard/asus/m2v-mx_se/romstage.c
View File

@ -49,6 +49,7 @@ unsigned int get_sbdn(unsigned bus);
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include <spd.h>
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
@ -128,11 +129,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
// Node 0
(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
// Node 1
(0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
(0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
};
unsigned bsp_apicid = 0;
int needs_reset = 0;

9
src/mainboard/asus/m2v/romstage.c
View File

@ -49,6 +49,7 @@ unsigned int get_sbdn(unsigned bus);
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include <spd.h>
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
@ -231,11 +232,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
// Node 0
(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
// Node 1
(0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
(0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
};
unsigned bsp_apicid = 0;
int needs_reset = 0;

1
src/mainboard/bcom/winnetp680/romstage.c
View File

@ -32,6 +32,7 @@
#include "pc80/udelay_io.c"
#include "lib/delay.c"
#include <lib.h>
#include <spd.h>
#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
#include "superio/winbond/w83697hf/w83697hf_early_serial.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)

10
src/mainboard/dell/s1850/romstage.c
View File

@ -19,6 +19,7 @@
#include "s1850_fixups.c"
#include "northbridge/intel/e7520/memory_initialized.c"
#include "cpu/x86/bist.h"
#include <spd.h>
#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC8374_SP1)
@ -149,10 +150,7 @@ static void main(unsigned long bist)
u16 w;
u32 l;
int do_reset;
/*
*
*
*/
static const struct mem_controller mch[] = {
{
.node_id = 0,
@ -164,8 +162,8 @@ static void main(unsigned long bist)
*/
/* the wiring on this part is really messed up */
/* this is my best guess so far */
.channel0 = {(0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, (0xa<<3)|3, },
.channel1 = {(0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, (0xa<<3)|7, },
.channel0 = {DIMM0, DIMM1, DIMM2, DIMM3, },
.channel1 = {DIMM4, DIMM5, DIMM6, DIMM7, },
}
};

3
src/mainboard/digitallogic/adl855pc/romstage.c
View File

@ -15,6 +15,7 @@
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include <spd.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@ -32,7 +33,7 @@ void main(unsigned long bist)
static const struct mem_controller memctrl[] = {
{
.d0 = PCI_DEV(0, 0, 1),
.channel0 = { (0xa<<3)|0, 0 },
.channel0 = { DIMM0, 0 },
},
};

2
src/mainboard/digitallogic/msm800sev/romstage.c
View File

@ -45,7 +45,7 @@ void main(unsigned long bist)
post_code(0x01);
static const struct mem_controller memctrl [] = {
{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
{.channel0 = {DIMM0, DIMM1}}
};
SystemPreInit();

9
src/mainboard/gigabyte/ga_2761gxdk/romstage.c
View File

@ -37,6 +37,7 @@
#include <console/console.h>
#include <usbdebug.h>
#include <spd.h>
#include <cpu/amd/model_fxx_rev.h>
@ -134,11 +135,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
// Node 0
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
(0xa<<3)|1, (0xa<<3)|3, 0, 0,
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
// Node 1
(0xa<<3)|4, (0xa<<3)|6, 0, 0,
(0xa<<3)|5, (0xa<<3)|7, 0, 0,
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE +

9
src/mainboard/gigabyte/m57sli/romstage.c
View File

@ -35,6 +35,7 @@
#include <console/console.h>
#include <usbdebug.h>
#include <spd.h>
#include <cpu/amd/model_fxx_rev.h>
@ -131,11 +132,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
// Node 0
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
(0xa<<3)|1, (0xa<<3)|3, 0, 0,
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
// Node 1
(0xa<<3)|4, (0xa<<3)|6, 0, 0,
(0xa<<3)|5, (0xa<<3)|7, 0, 0,
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE

4
src/mainboard/hp/dl145_g3/romstage.c
View File

@ -146,8 +146,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
// first node
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
// second node
DIMM4, DIMM6, 0, 0,

9
src/mainboard/ibm/e325/romstage.c
View File

@ -25,6 +25,7 @@
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include <spd.h>
#define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
@ -87,8 +88,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
.f1 = PCI_DEV(0, 0x18, 1),
.f2 = PCI_DEV(0, 0x18, 2),
.f3 = PCI_DEV(0, 0x18, 3),
.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
.channel0 = { DIMM0, DIMM2, 0, 0 },
.channel1 = { DIMM1, DIMM3, 0, 0 },
},
#if CONFIG_MAX_PHYSICAL_CPUS > 1
{
@ -97,8 +98,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
.f1 = PCI_DEV(0, 0x19, 1),
.f2 = PCI_DEV(0, 0x19, 2),
.f3 = PCI_DEV(0, 0x19, 3),
.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
.channel0 = { DIMM4, DIMM6, 0, 0 },
.channel1 = { DIMM5, DIMM7, 0, 0 },
},
#endif
};

9
src/mainboard/ibm/e326/romstage.c
View File

@ -29,6 +29,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
#include <spd.h>
static void memreset_setup(void)
{
@ -87,8 +88,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
.f1 = PCI_DEV(0, 0x18, 1),
.f2 = PCI_DEV(0, 0x18, 2),
.f3 = PCI_DEV(0, 0x18, 3),
.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
.channel0 = { DIMM0, DIMM2, 0, 0 },
.channel1 = { DIMM1, DIMM3, 0, 0 },
},
#if CONFIG_MAX_PHYSICAL_CPUS > 1
{
@ -97,8 +98,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
.f1 = PCI_DEV(0, 0x19, 1),
.f2 = PCI_DEV(0, 0x19, 2),
.f3 = PCI_DEV(0, 0x19, 3),
.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
.channel0 = { DIMM4, DIMM6, 0, 0 },
.channel1 = { DIMM5, DIMM7, 0, 0 },
},
#endif
};

2
src/mainboard/iei/pcisa-lx-800-r10/romstage.c
View File

@ -69,7 +69,7 @@ void main(unsigned long bist)
post_code(0x01);
static const struct mem_controller memctrl[] = {
{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
{.channel0 = {DIMM0, DIMM1}}
};
SystemPreInit();

5
src/mainboard/intel/eagleheights/romstage.c
View File

@ -78,6 +78,7 @@ static inline int spd_read_byte(u16 device, u8 address)
#include "lib/generic_sdram.c"
#include "northbridge/intel/i3100/reset_test.c"
#include "debug.c"
#include <spd.h>
#define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1)
@ -136,8 +137,8 @@ void main(unsigned long bist)
.f1 = PCI_DEV(0, 0x00, 1),
.f2 = PCI_DEV(0, 0x00, 2),
.f3 = PCI_DEV(0, 0x00, 3),
.channel0 = { (0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0 },
.channel1 = { (0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4 },
.channel0 = { DIMM3, DIMM2, DIMM1, DIMM0 },
.channel1 = { DIMM7, DIMM6, DIMM5, DIMM4 },
}
};

9
src/mainboard/intel/jarrell/romstage.c
View File

@ -19,6 +19,7 @@
#include "superio/nsc/pc87427/pc87427_early_init.c"
#include "northbridge/intel/e7520/memory_initialized.c"
#include "cpu/x86/bist.h"
#include <spd.h>
#define SIO_GPIO_BASE 0x680
#define SIO_XBUS_BASE 0x4880
@ -41,10 +42,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void main(unsigned long bist)
{
/*
*
*
*/
static const struct mem_controller mch[] = {
{
.node_id = 0,
@ -54,8 +51,8 @@ static void main(unsigned long bist)
.f2 = PCI_DEV(0, 0x00, 2),
.f3 = PCI_DEV(0, 0x00, 3),
*/
.channel0 = { (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, 0 },
.channel1 = { (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, 0 },
.channel0 = { DIMM2, DIMM1, DIMM0, 0 },
.channel1 = { DIMM6, DIMM5, DIMM4, 0 },
}
};

5
src/mainboard/intel/mtarvon/romstage.c
View File

@ -36,6 +36,7 @@
#include "superio/intel/i3100/i3100_early_serial.c"
#include "northbridge/intel/i3100/memory_initialized.c"
#include "cpu/x86/bist.h"
#include <spd.h>
#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0)
#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
@ -64,8 +65,8 @@ void main(unsigned long bist)
.f1 = PCI_DEV(0, 0x00, 1),
.f2 = PCI_DEV(0, 0x00, 2),
.f3 = PCI_DEV(0, 0x00, 3),
.channel0 = { (0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0 },
.channel1 = { (0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4 },
.channel0 = { DIMM3, DIMM2, DIMM1, DIMM0 },
.channel1 = { DIMM7, DIMM6, DIMM5, DIMM4 },
}
};

2
src/mainboard/intel/truxton/romstage.c
View File

@ -61,7 +61,7 @@ static void main(unsigned long bist)
{
.node_id = 0,
.f0 = PCI_DEV(0, 0x00, 0),
.channel0 = { (0xa<<3)|2, (0xa<<3)|3 },
.channel0 = { DIMM2, DIMM3 },
}
};

8
src/mainboard/intel/xe7501devkit/romstage.c
View File

@ -16,9 +16,9 @@
#include "superio/smsc/lpc47b272/lpc47b272_early_serial.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include <spd.h>
#define SUPERIO_PORT 0x2e
#define SERIAL_DEV PNP_DEV(SUPERIO_PORT, LPC47B272_SP1)
#define SERIAL_DEV PNP_DEV(0x2e, LPC47B272_SP1)
static void hard_reset(void)
{
@ -41,8 +41,8 @@ static void main(unsigned long bist)
{
.d0 = PCI_DEV(0, 0, 0),
.d0f1 = PCI_DEV(0, 0, 1),
.channel0 = { (0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, 0 },
.channel1 = { (0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, 0 },
.channel0 = { DIMM0, DIMM1, DIMM2, 0 },
.channel1 = { DIMM4, DIMM5, DIMM6, 0 },
},
};

1
src/mainboard/jetway/j7f24/romstage.c
View File

@ -34,6 +34,7 @@
#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
#include "superio/fintek/f71805f/f71805f_early_serial.c"
#include <lib.h>
#include <spd.h>
#if CONFIG_TTYS0_BASE == 0x2f8
#define SERIAL_DEV PNP_DEV(0x2e, F71805F_SP2)

3
src/mainboard/lanner/em8510/romstage.c
View File

@ -27,6 +27,7 @@
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <stdlib.h>
#include <spd.h>
#include "pc80/udelay_io.c"
#include <pc80/mc146818rtc.h>
#include <console/console.h>
@ -54,7 +55,7 @@ void main(unsigned long bist)
static const struct mem_controller memctrl[] = {
{
.d0 = PCI_DEV(0, 0, 1),
.channel0 = { (0xa<<3)|0, 0 },
.channel0 = { DIMM0, 0 },
},
};

3
src/mainboard/lippert/frontrunner/romstage.c
View File

@ -11,7 +11,6 @@
#include <cpu/amd/gx2def.h>
#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5535/cs5535.h"
#include <spd.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@ -76,7 +75,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
void main(unsigned long bist)
{
static const struct mem_controller memctrl [] = {
{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
{.channel0 = {DIMM0, DIMM1}}
};
unsigned char temp;
SystemPreInit();

2
src/mainboard/lippert/hurricane-lx/romstage.c
View File

@ -122,7 +122,7 @@ void main(unsigned long bist)
post_code(0x01);
static const struct mem_controller memctrl[] = {
{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
{.channel0 = {DIMM0, DIMM1}}
};
SystemPreInit();

3
src/mainboard/lippert/literunner-lx/romstage.c
View File

@ -34,7 +34,6 @@
#include <cpu/amd/lxdef.h>
#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
@ -166,7 +165,7 @@ void main(unsigned long bist)
post_code(0x01);
static const struct mem_controller memctrl[] = {
{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
{.channel0 = {DIMM0, DIMM1}}
};
SystemPreInit();

2
src/mainboard/lippert/roadrunner-lx/romstage.c
View File

@ -97,7 +97,7 @@ void main(unsigned long bist)
post_code(0x01);
static const struct mem_controller memctrl[] = {
{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
{.channel0 = {DIMM0, DIMM1}}
};
SystemPreInit();

3
src/mainboard/lippert/spacerunner-lx/romstage.c
View File

@ -34,7 +34,6 @@
#include <cpu/amd/lxdef.h>
#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
@ -163,7 +162,7 @@ void main(unsigned long bist)
post_code(0x01);
static const struct mem_controller memctrl[] = {
{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
{.channel0 = {DIMM0, DIMM1}}
};
SystemPreInit();

3
src/mainboard/msi/ms7135/romstage.c
View File

@ -49,6 +49,7 @@
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
static void memreset(int controllers, const struct mem_controller *ctrl)
{
@ -95,7 +96,7 @@ static void sio_setup(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
(0xa << 3) | 0, (0xa << 3) | 1, 0, 0,
DIMM0, DIMM1, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,

9
src/mainboard/msi/ms7260/romstage.c
View File

@ -42,6 +42,7 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#include <lib.h>
#include <spd.h>
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
@ -117,11 +118,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
// Node 0
(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
// Node 1
(0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
(0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE

6
src/mainboard/msi/ms9185/romstage.c
View File

@ -109,9 +109,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
//first node
RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6,
RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7,
//first node
RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6,
RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7,
//second node
RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,

9
src/mainboard/msi/ms9282/romstage.c
View File

@ -45,6 +45,7 @@
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include <spd.h>
#include "northbridge/amd/amdk8/setup_resource_map.c"
@ -132,11 +133,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
// Node 0
RC0|(0xa<<3)|0, RC0|(0xa<<3)|2, RC0|(0xa<<3)|4, RC0|(0xa<<3)|6,
RC0|(0xa<<3)|1, RC0|(0xa<<3)|3, RC0|(0xa<<3)|5, RC0|(0xa<<3)|7,
RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6,
RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7,
// node 1
RC1|(0xa<<3)|0, RC1|(0xa<<3)|2, RC1|(0xa<<3)|4, RC1|(0xa<<3)|6,
RC1|(0xa<<3)|1, RC1|(0xa<<3)|3, RC1|(0xa<<3)|5, RC1|(0xa<<3)|7,
RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
};
unsigned bsp_apicid = 0;

9
src/mainboard/newisys/khepri/romstage.c
View File

@ -14,6 +14,7 @@
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <lib.h>
#include <spd.h>
#include <cpu/amd/model_fxx_rev.h>
@ -93,11 +94,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
(0xa<<3)|1, (0xa<<3)|3, 0, 0,
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
(0xa<<3)|4, (0xa<<3)|6, 0, 0,
(0xa<<3)|5, (0xa<<3)|7, 0, 0,
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
#endif
};

9
src/mainboard/nvidia/l1_2pvv/romstage.c
View File

@ -36,6 +36,7 @@
#include <console/console.h>
#include <usbdebug.h>
#include <lib.h>
#include <spd.h>
#include <cpu/amd/model_fxx_rev.h>
@ -132,11 +133,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
// Node 0
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
(0xa<<3)|1, (0xa<<3)|3, 0, 0,
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
// Node 1
(0xa<<3)|4, (0xa<<3)|6, 0, 0,
(0xa<<3)|5, (0xa<<3)|7, 0, 0,
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE

1
src/mainboard/pcengines/alix1c/romstage.c
View File

@ -32,7 +32,6 @@
#include <cpu/amd/lxdef.h>
#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)

1
src/mainboard/pcengines/alix2d/romstage.c
View File

@ -32,7 +32,6 @@
#include <cpu/amd/lxdef.h>
#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)

9
src/mainboard/sunw/ultra40/romstage.c
View File

@ -8,6 +8,7 @@
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <lib.h>
#include <spd.h>
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
@ -117,11 +118,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
// Node 0
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
(0xa<<3)|1, (0xa<<3)|3, 0, 0,
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
// Node 1
(0xa<<3)|4, (0xa<<3)|6, 0, 0,
(0xa<<3)|5, (0xa<<3)|7, 0, 0,
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
};
int needs_reset;

17
src/mainboard/supermicro/h8dme/romstage.c
View File

@ -32,6 +32,7 @@
#include <console/console.h>
#include <lib.h>
#include <spd.h>
#include <cpu/amd/model_fxx_rev.h>
@ -188,15 +189,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
static const uint16_t spd_addr[] = {
// Node 0
RC0 | (0xa << 3) | 0, RC0 | (0xa << 3) | 2,
RC0 | (0xa << 3) | 4, RC0 | (0xa << 3) | 6,
RC0 | (0xa << 3) | 1, RC0 | (0xa << 3) | 3,
RC0 | (0xa << 3) | 5, RC0 | (0xa << 3) | 7,
RC0 | DIMM0, RC0 | DIMM2,
RC0 | DIMM4, RC0 | DIMM6,
RC0 | DIMM1, RC0 | DIMM3,
RC0 | DIMM5, RC0 | DIMM7,
// Node 1
RC1 | (0xa << 3) | 0, RC1 | (0xa << 3) | 2,
RC1 | (0xa << 3) | 4, RC1 | (0xa << 3) | 6,
RC1 | (0xa << 3) | 1, RC1 | (0xa << 3) | 3,
RC1 | (0xa << 3) | 5, RC1 | (0xa << 3) | 7,
RC1 | DIMM0, RC1 | DIMM2,
RC1 | DIMM4, RC1 | DIMM6,
RC1 | DIMM1, RC1 | DIMM3,
RC1 | DIMM5, RC1 | DIMM7,
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE

9
src/mainboard/supermicro/h8dmr/romstage.c
View File

@ -35,6 +35,7 @@
#include <console/console.h>
#include <lib.h>
#include <spd.h>
#include <cpu/amd/model_fxx_rev.h>
@ -124,11 +125,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
// Node 0
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
(0xa<<3)|1, (0xa<<3)|3, 0, 0,
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
// Node 1
(0xa<<3)|4, (0xa<<3)|6, 0, 0,
(0xa<<3)|5, (0xa<<3)|7, 0, 0,
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE

9
src/mainboard/supermicro/x6dai_g/romstage.c
View File

@ -20,6 +20,7 @@
#include "superio/winbond/w83627hf/w83627hf_early_init.c"
#include "northbridge/intel/e7525/memory_initialized.c"
#include "cpu/x86/bist.h"
#include <spd.h>
#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2)
@ -44,10 +45,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void main(unsigned long bist)
{
/*
*
*
*/
static const struct mem_controller mch[] = {
{
.node_id = 0,
@ -55,8 +52,8 @@ static void main(unsigned long bist)
.f1 = PCI_DEV(0, 0x00, 1),
.f2 = PCI_DEV(0, 0x00, 2),
.f3 = PCI_DEV(0, 0x00, 3),
.channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, },
.channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, },
.channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, },
.channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, },
}
};

5
src/mainboard/supermicro/x6dhe_g/romstage.c
View File

@ -21,6 +21,7 @@
#include "superio/winbond/w83627hf/w83627hf_early_init.c"
#include "northbridge/intel/e7520/memory_initialized.c"
#include "cpu/x86/bist.h"
#include <spd.h>
#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2)
@ -58,8 +59,8 @@ static void main(unsigned long bist)
.f2 = PCI_DEV(0, 0x00, 2),
.f3 = PCI_DEV(0, 0x00, 3),
*/
.channel0 = {(0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, (0xa<<3)|3, },
.channel1 = {(0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, (0xa<<3)|7, },
.channel0 = {DIMM0, DIMM1, DIMM2, DIMM3, },
.channel1 = {DIMM4, DIMM5, DIMM6, DIMM7, },
}
};

9
src/mainboard/supermicro/x6dhe_g2/romstage.c
View File

@ -19,6 +19,7 @@
#include "superio/nsc/pc87427/pc87427_early_init.c"
#include "northbridge/intel/e7520/memory_initialized.c"
#include "cpu/x86/bist.h"
#include <spd.h>
#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP1)
#define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP2)
@ -43,10 +44,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void main(unsigned long bist)
{
/*
*
*
*/
static const struct mem_controller mch[] = {
{
.node_id = 0,
@ -56,8 +53,8 @@ static void main(unsigned long bist)
.f2 = PCI_DEV(0, 0x00, 2),
.f3 = PCI_DEV(0, 0x00, 3),
*/
.channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, },
.channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, },
.channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, },
.channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, },
}
};

5
src/mainboard/supermicro/x6dhr_ig/romstage.c
View File

@ -19,6 +19,7 @@
#include "superio/winbond/w83627hf/w83627hf_early_init.c"
#include "northbridge/intel/e7520/memory_initialized.c"
#include "cpu/x86/bist.h"
#include <spd.h>
#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2)
@ -57,8 +58,8 @@ static void main(unsigned long bist)
.f2 = PCI_DEV(0, 0x00, 2),
.f3 = PCI_DEV(0, 0x00, 3),
*/
.channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, },
.channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, },
.channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, },
.channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, },
}
};

9
src/mainboard/supermicro/x6dhr_ig2/romstage.c
View File

@ -19,6 +19,7 @@
#include "superio/winbond/w83627hf/w83627hf_early_init.c"
#include "northbridge/intel/e7520/memory_initialized.c"
#include "cpu/x86/bist.h"
#include <spd.h>
#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2)
@ -44,10 +45,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void main(unsigned long bist)
{
/*
*
*
*/
static const struct mem_controller mch[] = {
{
.node_id = 0,
@ -57,8 +54,8 @@ static void main(unsigned long bist)
.f2 = PCI_DEV(0, 0x00, 2),
.f3 = PCI_DEV(0, 0x00, 3),
*/
.channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, },
.channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, },
.channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, },
.channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, },
}
};

2
src/mainboard/traverse/geos/romstage.c
View File

@ -63,7 +63,7 @@ void main(unsigned long bist)
post_code(0x01);
static const struct mem_controller memctrl[] = {
{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
{.channel0 = {DIMM0, DIMM1}}
};
SystemPreInit();

5
src/mainboard/tyan/s2735/romstage.c
View File

@ -9,6 +9,7 @@
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <lib.h>
#include <spd.h>
#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
#include "northbridge/intel/e7501/raminit.h"
@ -44,8 +45,8 @@ void main(unsigned long bist)
{
.d0 = PCI_DEV(0, 0, 0),
.d0f1 = PCI_DEV(0, 0, 1),
.channel0 = { (0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, 0 },
.channel1 = { (0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, 0 },
.channel0 = { DIMM0, DIMM1, DIMM2, 0 },
.channel1 = { DIMM4, DIMM5, DIMM6, 0 },
},
};

5
src/mainboard/tyan/s2850/romstage.c
View File

@ -9,6 +9,7 @@
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <lib.h>
#include <spd.h>
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
@ -86,8 +87,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
.f1 = PCI_DEV(0, 0x18, 1),
.f2 = PCI_DEV(0, 0x18, 2),
.f3 = PCI_DEV(0, 0x18, 3),
.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
.channel0 = { DIMM0, DIMM2, 0, 0 },
.channel1 = { DIMM1, DIMM3, 0, 0 },
},
};

9
src/mainboard/tyan/s2875/romstage.c
View File

@ -9,6 +9,7 @@
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <lib.h>
#include <spd.h>
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
@ -87,8 +88,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
.f1 = PCI_DEV(0, 0x18, 1),
.f2 = PCI_DEV(0, 0x18, 2),
.f3 = PCI_DEV(0, 0x18, 3),
.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
.channel0 = { DIMM0, DIMM2, 0, 0 },
.channel1 = { DIMM1, DIMM3, 0, 0 },
},
#if CONFIG_MAX_PHYSICAL_CPUS > 1
{
@ -97,8 +98,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
.f1 = PCI_DEV(0, 0x19, 1),
.f2 = PCI_DEV(0, 0x19, 2),
.f3 = PCI_DEV(0, 0x19, 3),
.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
.channel0 = { DIMM4, DIMM6, 0, 0 },
.channel1 = { DIMM5, DIMM7, 0, 0 },
},
#endif
};

9
src/mainboard/tyan/s2880/romstage.c
View File

@ -9,6 +9,7 @@
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <lib.h>
#include <spd.h>
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
@ -87,8 +88,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
.f1 = PCI_DEV(0, 0x18, 1),
.f2 = PCI_DEV(0, 0x18, 2),
.f3 = PCI_DEV(0, 0x18, 3),
.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
.channel0 = { DIMM0, DIMM2, 0, 0 },
.channel1 = { DIMM1, DIMM3, 0, 0 },
},
#if CONFIG_MAX_PHYSICAL_CPUS > 1
{
@ -97,8 +98,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
.f1 = PCI_DEV(0, 0x19, 1),
.f2 = PCI_DEV(0, 0x19, 2),
.f3 = PCI_DEV(0, 0x19, 3),
.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
.channel0 = { DIMM4, DIMM6, 0, 0 },
.channel1 = { DIMM5, DIMM7, 0, 0 },
},
#endif
};

9
src/mainboard/tyan/s2881/romstage.c
View File

@ -8,6 +8,7 @@
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <lib.h>
#include <spd.h>
#include <cpu/amd/model_fxx_rev.h>
@ -80,11 +81,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
(0xa<<3)|1, (0xa<<3)|3, 0, 0,
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
(0xa<<3)|4, (0xa<<3)|6, 0, 0,
(0xa<<3)|5, (0xa<<3)|7, 0, 0,
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
#endif
};

9
src/mainboard/tyan/s2882/romstage.c
View File

@ -9,6 +9,7 @@
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <lib.h>
#include <spd.h>
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
@ -85,8 +86,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
.f1 = PCI_DEV(0, 0x18, 1),
.f2 = PCI_DEV(0, 0x18, 2),
.f3 = PCI_DEV(0, 0x18, 3),
.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
.channel0 = { DIMM0, DIMM2, 0, 0 },
.channel1 = { DIMM1, DIMM3, 0, 0 },
},
#if CONFIG_MAX_PHYSICAL_CPUS > 1
{
@ -95,8 +96,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
.f1 = PCI_DEV(0, 0x19, 1),
.f2 = PCI_DEV(0, 0x19, 2),
.f3 = PCI_DEV(0, 0x19, 3),
.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
.channel0 = { DIMM4, DIMM6, 0, 0 },
.channel1 = { DIMM5, DIMM7, 0, 0 },
},
#endif
};

9
src/mainboard/tyan/s2885/romstage.c
View File

@ -8,6 +8,7 @@
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <lib.h>
#include <spd.h>
#include <cpu/amd/model_fxx_rev.h>
@ -83,11 +84,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
(0xa<<3)|1, (0xa<<3)|3, 0, 0,
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
(0xa<<3)|4, (0xa<<3)|6, 0, 0,
(0xa<<3)|5, (0xa<<3)|7, 0, 0,
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
#endif
};

9
src/mainboard/tyan/s2891/romstage.c
View File

@ -8,6 +8,7 @@
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <lib.h>
#include <spd.h>
#include <cpu/amd/model_fxx_rev.h>
@ -93,11 +94,11 @@ static void sio_setup(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
(0xa<<3)|1, (0xa<<3)|3, 0, 0,
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
(0xa<<3)|4, (0xa<<3)|6, 0, 0,
(0xa<<3)|5, (0xa<<3)|7, 0, 0,
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
#endif
};

9
src/mainboard/tyan/s2892/romstage.c
View File

@ -9,6 +9,7 @@
#include <console/console.h>
#include <lib.h>
#include <spd.h>
#include <cpu/amd/model_fxx_rev.h>
@ -88,11 +89,11 @@ static void sio_setup(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
(0xa<<3)|1, (0xa<<3)|3, 0, 0,
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
(0xa<<3)|4, (0xa<<3)|6, 0, 0,
(0xa<<3)|5, (0xa<<3)|7, 0, 0,
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
#endif
};

9
src/mainboard/tyan/s2895/romstage.c
View File

@ -8,6 +8,7 @@
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <lib.h>
#include <spd.h>
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/nvidia/ck804/ck804_early_smbus.h"
@ -112,10 +113,10 @@ static void sio_setup(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const u16 spd_addr [] = {
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
(0xa<<3)|1, (0xa<<3)|3, 0, 0,
(0xa<<3)|4, (0xa<<3)|6, 0, 0,
(0xa<<3)|5, (0xa<<3)|7, 0, 0,
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
};
int needs_reset;

9
src/mainboard/tyan/s2912/romstage.c
View File

@ -35,6 +35,7 @@
#include <console/console.h>
#include <lib.h>
#include <spd.h>
#include <usbdebug.h>
#include <cpu/amd/model_fxx_rev.h>
@ -130,11 +131,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
// Node 0
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
(0xa<<3)|1, (0xa<<3)|3, 0, 0,
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
// Node 1
(0xa<<3)|4, (0xa<<3)|6, 0, 0,
(0xa<<3)|5, (0xa<<3)|7, 0, 0,
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE

1
src/mainboard/via/epia-cn/romstage.c
View File

@ -34,6 +34,7 @@
#include "lib/delay.c"
#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
#include "southbridge/via/vt8235/vt8235_early_serial.c"
#include <spd.h>
static inline int spd_read_byte(unsigned device, unsigned address)
{

5
src/mainboard/via/epia-n/romstage.c
View File

@ -36,13 +36,10 @@
#include "cpu/x86/lapic/boot_cpu.c"
#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
#include "superio/winbond/w83697hf/w83697hf_early_serial.c"
#include <spd.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
/*
* NOOB ::
* d0f0 - Device 0 Function 0 etc.
*/
static const struct mem_controller ctrl = {
.d0f0 = 0x0000,
.d0f2 = 0x2000,

1
src/mainboard/via/pc2500e/romstage.c
View File

@ -34,6 +34,7 @@
#include "lib/delay.c"
#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
#include "superio/ite/it8716f/it8716f_early_serial.c"
#include <spd.h>
#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)

1
src/mainboard/via/vt8454c/romstage.c
View File

@ -39,6 +39,7 @@
#include "northbridge/via/cx700/cx700_early_serial.c"
#include "northbridge/via/cx700/raminit.c"
#include <spd.h>
static void enable_mainboard_devices(void)
{

2
src/mainboard/winent/pl6064/romstage.c
View File

@ -67,7 +67,7 @@ void main(unsigned long bist)
post_code(0x01);
static const struct mem_controller memctrl[] = {
{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
{.channel0 = {DIMM0, DIMM1}}
};
SystemPreInit();

2
src/mainboard/wyse/s50/romstage.c
View File

@ -54,7 +54,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
void main(unsigned long bist)
{
static const struct mem_controller memctrl [] = {
{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
{.channel0 = {DIMM0, DIMM1}}
};
SystemPreInit();