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treewide: capitalize 'BIOS' 

Also replace 'BIOS' by coreboot when the image is 'coreboot.rom'.

Change-Id: I8303b7baa9671f19a036a59775026ffd63c85273
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Elyes HAOUAS 2020-02-16 16:22:52 +01:00 committed by Patrick Georgi
parent c7a3152273
commit 6dc9d0352e
22 changed files with 30 additions and 30 deletions
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2
Documentation/releases/coreboot-4.8.1-relnotes.md
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@ -40,7 +40,7 @@ possible
Lenovo mainboards Lenovo mainboards
----------------- -----------------
* Started integration of VBT (Video Bios Table) binary files to * Started integration of VBT (Video BIOS Table) binary files to
support native graphics initialisation support native graphics initialisation
Internal changes Internal changes

2
Documentation/soc/intel/fit.md
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@ -57,4 +57,4 @@ execution of the IA32 reset vector happens.
## References ## References
* [Intel TXT LAB handout](https://downloadmirror.intel.com/18931/eng/Intel%20TXT%20LAB%20Handout.pdf) * [Intel TXT LAB handout](https://downloadmirror.intel.com/18931/eng/Intel%20TXT%20LAB%20Handout.pdf)
* [FIT bios specification](https://www.intel.com/content/dam/www/public/us/en/documents/guides/fit-bios-specification.pdf) * [FIT BIOS specification](https://www.intel.com/content/dam/www/public/us/en/documents/guides/fit-bios-specification.pdf)

2
Documentation/tutorial/part1.md
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@ -173,7 +173,7 @@ Here's the command line instruction broken down:
This starts the QEMU emulator with the i440FX host PCI bridge and PIIX3 PCI to This starts the QEMU emulator with the i440FX host PCI bridge and PIIX3 PCI to
ISA bridge. ISA bridge.
* `-bios build/coreboot.rom` * `-bios build/coreboot.rom`
Use the bios rom image that we just built. If this flag is left out, the Use the coreboot rom image that we just built. If this flag is left out, the
standard SeaBIOS image that comes with QEMU is used. standard SeaBIOS image that comes with QEMU is used.
* `-serial stdio` * `-serial stdio`
Send the serial output to the console. This allows you to view the coreboot Send the serial output to the console. This allows you to view the coreboot

2
payloads/external/SeaBIOS/Kconfig vendored
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@ -125,7 +125,7 @@ config SEABIOS_DEBUG_LEVEL
level 1 - Basic output, interrupts 5, 18h, 19h, 40h, SMP, PNP, PMM level 1 - Basic output, interrupts 5, 18h, 19h, 40h, SMP, PNP, PMM
level 2 - AHCI, Floppy, Basic ps2, interrupts 11h, 12h, 14h, 17h level 2 - AHCI, Floppy, Basic ps2, interrupts 11h, 12h, 14h, 17h
level 3 - bootsplash, initializations, SeaBIOS VGA BIOS interrupts level 3 - bootsplash, initializations, SeaBIOS VGA BIOS interrupts
level 4 - bios tables, more optionrom level 4 - BIOS tables, more optionrom
level 5 - Extra bootsplash, more XHCI level 5 - Extra bootsplash, more XHCI
level 6 - ATA commands, extra optionrom level 6 - ATA commands, extra optionrom
level 7 - extra ps2 commands, more OHCI & EHCI level 7 - extra ps2 commands, more OHCI & EHCI

2
src/cpu/x86/smm/smm_module_loader.c
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@ -396,7 +396,7 @@ int smm_load_module(void *smram, size_t size, struct smm_loader_params *params)
/* Does the required amount of memory exceed the SMRAM region size? */ /* Does the required amount of memory exceed the SMRAM region size? */
total_size = total_stack_size + handler_size; total_size = total_stack_size + handler_size;
total_size += fxsave_size + SMM_DEFAULT_SIZE; total_size += fxsave_size + SMM_DEFAULT_SIZE;
// account for the bios resource list // account for the BIOS resource list
if (CONFIG(STM)) if (CONFIG(STM))
total_size += CONFIG_BIOS_RESOURCE_LIST_SIZE; total_size += CONFIG_BIOS_RESOURCE_LIST_SIZE;

2
src/device/Kconfig
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@ -721,7 +721,7 @@ config INTEL_GMA_HAVE_VBT
config INTEL_GMA_ADD_VBT config INTEL_GMA_ADD_VBT
depends on SOC_INTEL_COMMON || CPU_INTEL_COMMON depends on SOC_INTEL_COMMON || CPU_INTEL_COMMON
bool "Add a Video Bios Table (VBT) binary to CBFS" bool "Add a Video BIOS Table (VBT) binary to CBFS"
default y if INTEL_GMA_HAVE_VBT default y if INTEL_GMA_HAVE_VBT
help help
Add a VBT data file to CBFS. The VBT describes the integrated Add a VBT data file to CBFS. The VBT describes the integrated

2
src/device/oprom/include/x86emu/x86emu.h
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@ -170,7 +170,7 @@ void X86EMU_halt_sys(void);
#define DEBUG_SVC_F 0x000020 #define DEBUG_SVC_F 0x000020
#define DEBUG_FS_F 0x000080 #define DEBUG_FS_F 0x000080
#define DEBUG_PROC_F 0x000100 #define DEBUG_PROC_F 0x000100
#define DEBUG_SYSINT_F 0x000200 /* bios system interrupts. */ #define DEBUG_SYSINT_F 0x000200 /* BIOS system interrupts. */
#define DEBUG_TRACECALL_F 0x000400 #define DEBUG_TRACECALL_F 0x000400
#define DEBUG_INSTRUMENT_F 0x000800 #define DEBUG_INSTRUMENT_F 0x000800
#define DEBUG_MEM_TRACE_F 0x001000 #define DEBUG_MEM_TRACE_F 0x001000

2
src/drivers/intel/gma/int15.c
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@ -33,7 +33,7 @@ int intel_vga_int15_handler(void)
* bit 2 = Graphics Stretching * bit 2 = Graphics Stretching
* bit 1 = Text Stretching * bit 1 = Text Stretching
* bit 0 = Centering (do not set with bit1 or bit2) * bit 0 = Centering (do not set with bit1 or bit2)
* 0 = video bios default * 0 = video BIOS default
*/ */
X86_AX = 0x005f; X86_AX = 0x005f;
X86_CX = pfit; X86_CX = pfit;

2
src/mainboard/asus/p8z77-m_pro/cmos.layout
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@ -77,7 +77,7 @@ entries
421 2 e 8 usb3_mode 421 2 e 8 usb3_mode
# usb3_drv # usb3_drv
# Load (or not) pre-OS xHCI USB3 bios driver # Load (or not) pre-OS xHCI USB3 BIOS driver
# #
423 1 e 1 usb3_drv 423 1 e 1 usb3_drv

2
src/mainboard/asus/p8z77-m_pro/early_init.c
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@ -115,7 +115,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
.tseg_size = CONFIG_SMM_TSEG_SIZE, .tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* SMBus mul 2 */ .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* SMBus mul 2 */
.ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
.ec_present = 0, /* Asus 2203 bios shows XUECA016, but no EC */ .ec_present = 0, /* Asus 2203 BIOS shows XUECA016, but no EC */
.gbe_enable = 0, /* Board uses no Intel GbE but a RTL8111F */ .gbe_enable = 0, /* Board uses no Intel GbE but a RTL8111F */
.dimm_channel0_disabled = 0, /* Both DIMM enabled */ .dimm_channel0_disabled = 0, /* Both DIMM enabled */
.dimm_channel1_disabled = 0, /* Both DIMM enabled */ .dimm_channel1_disabled = 0, /* Both DIMM enabled */

4
src/mainboard/google/cyan/Kconfig
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@ -78,7 +78,7 @@ config VGA_BIOS_FILE
depends on VGA_BIOS depends on VGA_BIOS
default "3rdparty/blobs/mainboard/intel/strago/vgabios.bin" default "3rdparty/blobs/mainboard/intel/strago/vgabios.bin"
help help
The C0 version of the video bios gets computed from this name The C0 version of the video BIOS gets computed from this name
so that they can both be added. Only the correct one for the so that they can both be added. Only the correct one for the
system will be run. system will be run.
@ -87,7 +87,7 @@ config VGA_BIOS_ID
depends on VGA_BIOS depends on VGA_BIOS
default "8086,22b0" default "8086,22b0"
help help
The VGA_BIOS_ID for the C0 version of the video bios is hardcoded The VGA_BIOS_ID for the C0 version of the video BIOS is hardcoded
in soc/intel/braswell/Makefile.inc as 8086,22b1 in soc/intel/braswell/Makefile.inc as 8086,22b1
config CBFS_SIZE config CBFS_SIZE

6
src/mainboard/google/link/mainboard.c
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@ -47,10 +47,10 @@ static int int15_handler(void)
* bit 2 = Graphics Stretching * bit 2 = Graphics Stretching
* bit 1 = Text Stretching * bit 1 = Text Stretching
* bit 0 = Centering (do not set with bit1 or bit2) * bit 0 = Centering (do not set with bit1 or bit2)
* 0 = video bios default * 0 = video BIOS default
*/ */
X86_AX = 0x005f; X86_AX = 0x005f;
X86_CL = 0x00; /* Use video bios default */ X86_CL = 0x00; /* Use video BIOS default */
res = 1; res = 1;
break; break;
case 0x5f35: case 0x5f35:
@ -66,7 +66,7 @@ static int int15_handler(void)
* bit 7 = LFP2 * bit 7 = LFP2
*/ */
X86_AX = 0x005f; X86_AX = 0x005f;
X86_CX = 0x0000; /* Use video bios default */ X86_CX = 0x0000; /* Use video BIOS default */
res = 1; res = 1;
break; break;
case 0x5f51: case 0x5f51:

2
src/mainboard/google/rambi/mainboard.c
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@ -48,7 +48,7 @@ static int int15_handler(void)
* bit 2 = Graphics Stretching * bit 2 = Graphics Stretching
* bit 1 = Text Stretching * bit 1 = Text Stretching
* bit 0 = Centering (do not set with bit1 or bit2) * bit 0 = Centering (do not set with bit1 or bit2)
* 0 = video bios default * 0 = video BIOS default
*/ */
X86_AX = 0x005f; X86_AX = 0x005f;
X86_CX = 0x0001; X86_CX = 0x0001;

4
src/mainboard/intel/strago/Kconfig
View File

@ -35,7 +35,7 @@ config VGA_BIOS_FILE
depends on VGA_BIOS depends on VGA_BIOS
default "3rdparty/blobs/mainboard/intel/strago/vgabios.bin" default "3rdparty/blobs/mainboard/intel/strago/vgabios.bin"
help help
The C0 version of the video bios gets computed from this name The C0 version of the video BIOS gets computed from this name
so that they can both be added. Only the correct one for the so that they can both be added. Only the correct one for the
system will be run. system will be run.
@ -44,7 +44,7 @@ config VGA_BIOS_ID
depends on VGA_BIOS depends on VGA_BIOS
default "8086,22b0" default "8086,22b0"
help help
The VGA_BIOS_ID for the C0 version of the video bios is hardcoded The VGA_BIOS_ID for the C0 version of the video BIOS is hardcoded
in soc/intel/braswell/Makefile.inc as 8086,22b1 in soc/intel/braswell/Makefile.inc as 8086,22b1
config EC_GOOGLE_CHROMEEC_BOARDNAME config EC_GOOGLE_CHROMEEC_BOARDNAME

6
src/mainboard/kontron/ktqm77/mainboard.c
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@ -41,12 +41,12 @@ static int int15_handler(void)
* bit 2 = Graphics Stretching * bit 2 = Graphics Stretching
* bit 1 = Text Stretching * bit 1 = Text Stretching
* bit 0 = Centering (do not set with bit1 or bit2) * bit 0 = Centering (do not set with bit1 or bit2)
* 0 = video bios default * 0 = video BIOS default
*/ */
X86_EAX &= 0xffff0000; X86_EAX &= 0xffff0000;
X86_EAX |= 0x005f; X86_EAX |= 0x005f;
X86_ECX &= 0xffffff00; X86_ECX &= 0xffffff00;
X86_ECX |= 0x00; /* Use video bios default */ X86_ECX |= 0x00; /* Use video BIOS default */
res = 1; res = 1;
break; break;
case 0x5f35: case 0x5f35:
@ -64,7 +64,7 @@ static int int15_handler(void)
X86_EAX &= 0xffff0000; X86_EAX &= 0xffff0000;
X86_EAX |= 0x005f; X86_EAX |= 0x005f;
X86_ECX &= 0xffff0000; X86_ECX &= 0xffff0000;
X86_ECX |= 0x0000; /* Use video bios default */ X86_ECX |= 0x0000; /* Use video BIOS default */
res = 1; res = 1;
break; break;
case 0x5f51: case 0x5f51:

2
src/mainboard/lenovo/t420/early_init.c
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@ -48,7 +48,7 @@ static void hybrid_graphics_init(void)
pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
} }
// OC3 set in bios to port 2-7, OC7 set in bios to port 10-13 // OC3 set in BIOS to port 2-7, OC7 set in BIOS to port 10-13
const struct southbridge_usb_port mainboard_usb_ports[] = { const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 1, 0 }, /* P0: system port 4, OC0 */ { 1, 1, 0 }, /* P0: system port 4, OC0 */
{ 1, 1, 1 }, /* P1: system port 2 (EHCI debug), OC 1 */ { 1, 1, 1 }, /* P1: system port 2 (EHCI debug), OC 1 */

2
src/soc/intel/apollolake/chip.c
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@ -733,7 +733,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
/* Enable Audio clk gate and power gate */ /* Enable Audio clk gate and power gate */
silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable; silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable;
silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable; silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable;
/* Bios config lockdown Audio clk and power gate */ /* BIOS config lockdown Audio clk and power gate */
silconfig->BiosCfgLockDown = cfg->hdaudio_bios_config_lockdown; silconfig->BiosCfgLockDown = cfg->hdaudio_bios_config_lockdown;
if (CONFIG(SOC_INTEL_GLK)) if (CONFIG(SOC_INTEL_GLK))
glk_fsp_silicon_init_params_cb(cfg, silconfig); glk_fsp_silicon_init_params_cb(cfg, silconfig);

2
src/soc/intel/common/block/fast_spi/fast_spi.c
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@ -237,7 +237,7 @@ void fast_spi_cache_bios_region(void)
/* LOCAL APIC default address is 0xFEE0000, bios_size over 16MB will /* LOCAL APIC default address is 0xFEE0000, bios_size over 16MB will
* cause memory type conflict when setting memory type to write * cause memory type conflict when setting memory type to write
* protection, so limit the cached bios region to be no more than 16MB. * protection, so limit the cached BIOS region to be no more than 16MB.
* */ * */
bios_size = MIN(bios_size, 16 * MiB); bios_size = MIN(bios_size, 16 * MiB);
if (bios_size <= 0) if (bios_size <= 0)

6
src/soc/intel/common/pch/lockdown/lockdown.c
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@ -69,12 +69,12 @@ static void fast_spi_lockdown_cfg(int chipset_lockdown)
/* Lock FAST_SPIBAR */ /* Lock FAST_SPIBAR */
fast_spi_lock_bar(); fast_spi_lock_bar();
/* Set Bios Interface Lock, Bios Lock */ /* Set BIOS Interface Lock, BIOS Lock */
if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
/* Bios Interface Lock */ /* BIOS Interface Lock */
fast_spi_set_bios_interface_lock_down(); fast_spi_set_bios_interface_lock_down();
/* Bios Lock */ /* BIOS Lock */
fast_spi_set_lock_enable(); fast_spi_set_lock_enable();
} }
} }

2
src/soc/intel/skylake/lockdown.c
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@ -22,7 +22,7 @@
static void lpc_lockdown_config(int chipset_lockdown) static void lpc_lockdown_config(int chipset_lockdown)
{ {
/* Set Bios Interface Lock, Bios Lock */ /* Set BIOS Interface Lock, BIOS Lock */
if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
lpc_set_bios_interface_lock_down(); lpc_set_bios_interface_lock_down();
lpc_set_lock_enable(); lpc_set_lock_enable();

2
util/inteltool/inteltool.8
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@ -32,7 +32,7 @@ Show only GPIO register differences from hardware defaults.
Dump I/O Controller Hub (ICH) southbridge RCBA registers. Dump I/O Controller Hub (ICH) southbridge RCBA registers.
.TP .TP
.B "\-s, \-\-spi" .B "\-s, \-\-spi"
Dump I/O Controller Hub (ICH) southbridge SPI registers and bios control. Dump I/O Controller Hub (ICH) southbridge SPI registers and BIOS control.
.TP .TP
.B "\-f, \-\-gfx" .B "\-f, \-\-gfx"
.RB "Dump graphics registers. " \ .RB "Dump graphics registers. " \

2
util/inteltool/spi.c
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@ -22,7 +22,7 @@ static const io_register_t pch_bios_cntl_registers[] = {
{ 0x1, 1, "BLE - lock enable" }, { 0x1, 1, "BLE - lock enable" },
{ 0x2, 2, "SPI Read configuration" }, { 0x2, 2, "SPI Read configuration" },
{ 0x4, 1, "TopSwapStatus" }, { 0x4, 1, "TopSwapStatus" },
{ 0x5, 1, "SMM Bios Write Protect Disable" }, { 0x5, 1, "SMM BIOS Write Protect Disable" },
{ 0x6, 2, "reserved" }, { 0x6, 2, "reserved" },
}; };