treewide: capitalize 'BIOS'
Also replace 'BIOS' by coreboot when the image is 'coreboot.rom'. Change-Id: I8303b7baa9671f19a036a59775026ffd63c85273 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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@ -40,7 +40,7 @@ possible
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Lenovo mainboards
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-----------------
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* Started integration of VBT (Video Bios Table) binary files to
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* Started integration of VBT (Video BIOS Table) binary files to
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support native graphics initialisation
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Internal changes
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@ -57,4 +57,4 @@ execution of the IA32 reset vector happens.
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## References
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* [Intel TXT LAB handout](https://downloadmirror.intel.com/18931/eng/Intel%20TXT%20LAB%20Handout.pdf)
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* [FIT bios specification](https://www.intel.com/content/dam/www/public/us/en/documents/guides/fit-bios-specification.pdf)
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* [FIT BIOS specification](https://www.intel.com/content/dam/www/public/us/en/documents/guides/fit-bios-specification.pdf)
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@ -173,7 +173,7 @@ Here's the command line instruction broken down:
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This starts the QEMU emulator with the i440FX host PCI bridge and PIIX3 PCI to
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ISA bridge.
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* `-bios build/coreboot.rom`
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Use the bios rom image that we just built. If this flag is left out, the
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Use the coreboot rom image that we just built. If this flag is left out, the
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standard SeaBIOS image that comes with QEMU is used.
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* `-serial stdio`
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Send the serial output to the console. This allows you to view the coreboot
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@ -125,7 +125,7 @@ config SEABIOS_DEBUG_LEVEL
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level 1 - Basic output, interrupts 5, 18h, 19h, 40h, SMP, PNP, PMM
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level 2 - AHCI, Floppy, Basic ps2, interrupts 11h, 12h, 14h, 17h
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level 3 - bootsplash, initializations, SeaBIOS VGA BIOS interrupts
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level 4 - bios tables, more optionrom
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level 4 - BIOS tables, more optionrom
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level 5 - Extra bootsplash, more XHCI
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level 6 - ATA commands, extra optionrom
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level 7 - extra ps2 commands, more OHCI & EHCI
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@ -396,7 +396,7 @@ int smm_load_module(void *smram, size_t size, struct smm_loader_params *params)
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/* Does the required amount of memory exceed the SMRAM region size? */
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total_size = total_stack_size + handler_size;
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total_size += fxsave_size + SMM_DEFAULT_SIZE;
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// account for the bios resource list
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// account for the BIOS resource list
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if (CONFIG(STM))
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total_size += CONFIG_BIOS_RESOURCE_LIST_SIZE;
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@ -721,7 +721,7 @@ config INTEL_GMA_HAVE_VBT
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config INTEL_GMA_ADD_VBT
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depends on SOC_INTEL_COMMON || CPU_INTEL_COMMON
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bool "Add a Video Bios Table (VBT) binary to CBFS"
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bool "Add a Video BIOS Table (VBT) binary to CBFS"
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default y if INTEL_GMA_HAVE_VBT
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help
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Add a VBT data file to CBFS. The VBT describes the integrated
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@ -170,7 +170,7 @@ void X86EMU_halt_sys(void);
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#define DEBUG_SVC_F 0x000020
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#define DEBUG_FS_F 0x000080
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#define DEBUG_PROC_F 0x000100
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#define DEBUG_SYSINT_F 0x000200 /* bios system interrupts. */
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#define DEBUG_SYSINT_F 0x000200 /* BIOS system interrupts. */
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#define DEBUG_TRACECALL_F 0x000400
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#define DEBUG_INSTRUMENT_F 0x000800
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#define DEBUG_MEM_TRACE_F 0x001000
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@ -33,7 +33,7 @@ int intel_vga_int15_handler(void)
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* bit 2 = Graphics Stretching
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* bit 1 = Text Stretching
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* bit 0 = Centering (do not set with bit1 or bit2)
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* 0 = video bios default
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* 0 = video BIOS default
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*/
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X86_AX = 0x005f;
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X86_CX = pfit;
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@ -77,7 +77,7 @@ entries
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421 2 e 8 usb3_mode
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# usb3_drv
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# Load (or not) pre-OS xHCI USB3 bios driver
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# Load (or not) pre-OS xHCI USB3 BIOS driver
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#
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423 1 e 1 usb3_drv
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@ -115,7 +115,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
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.tseg_size = CONFIG_SMM_TSEG_SIZE,
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.spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* SMBus mul 2 */
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.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
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.ec_present = 0, /* Asus 2203 bios shows XUECA016, but no EC */
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.ec_present = 0, /* Asus 2203 BIOS shows XUECA016, but no EC */
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.gbe_enable = 0, /* Board uses no Intel GbE but a RTL8111F */
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.dimm_channel0_disabled = 0, /* Both DIMM enabled */
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.dimm_channel1_disabled = 0, /* Both DIMM enabled */
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@ -78,7 +78,7 @@ config VGA_BIOS_FILE
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depends on VGA_BIOS
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default "3rdparty/blobs/mainboard/intel/strago/vgabios.bin"
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help
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The C0 version of the video bios gets computed from this name
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The C0 version of the video BIOS gets computed from this name
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so that they can both be added. Only the correct one for the
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system will be run.
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@ -87,7 +87,7 @@ config VGA_BIOS_ID
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depends on VGA_BIOS
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default "8086,22b0"
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help
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The VGA_BIOS_ID for the C0 version of the video bios is hardcoded
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The VGA_BIOS_ID for the C0 version of the video BIOS is hardcoded
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in soc/intel/braswell/Makefile.inc as 8086,22b1
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config CBFS_SIZE
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@ -47,10 +47,10 @@ static int int15_handler(void)
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* bit 2 = Graphics Stretching
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* bit 1 = Text Stretching
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* bit 0 = Centering (do not set with bit1 or bit2)
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* 0 = video bios default
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* 0 = video BIOS default
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*/
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X86_AX = 0x005f;
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X86_CL = 0x00; /* Use video bios default */
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X86_CL = 0x00; /* Use video BIOS default */
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res = 1;
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break;
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case 0x5f35:
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@ -66,7 +66,7 @@ static int int15_handler(void)
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* bit 7 = LFP2
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*/
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X86_AX = 0x005f;
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X86_CX = 0x0000; /* Use video bios default */
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X86_CX = 0x0000; /* Use video BIOS default */
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res = 1;
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break;
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case 0x5f51:
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@ -48,7 +48,7 @@ static int int15_handler(void)
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* bit 2 = Graphics Stretching
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* bit 1 = Text Stretching
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* bit 0 = Centering (do not set with bit1 or bit2)
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* 0 = video bios default
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* 0 = video BIOS default
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*/
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X86_AX = 0x005f;
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X86_CX = 0x0001;
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@ -35,7 +35,7 @@ config VGA_BIOS_FILE
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depends on VGA_BIOS
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default "3rdparty/blobs/mainboard/intel/strago/vgabios.bin"
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help
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The C0 version of the video bios gets computed from this name
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The C0 version of the video BIOS gets computed from this name
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so that they can both be added. Only the correct one for the
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system will be run.
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depends on VGA_BIOS
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default "8086,22b0"
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help
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The VGA_BIOS_ID for the C0 version of the video bios is hardcoded
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The VGA_BIOS_ID for the C0 version of the video BIOS is hardcoded
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in soc/intel/braswell/Makefile.inc as 8086,22b1
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config EC_GOOGLE_CHROMEEC_BOARDNAME
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@ -41,12 +41,12 @@ static int int15_handler(void)
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* bit 2 = Graphics Stretching
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* bit 1 = Text Stretching
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* bit 0 = Centering (do not set with bit1 or bit2)
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* 0 = video bios default
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* 0 = video BIOS default
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*/
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X86_EAX &= 0xffff0000;
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X86_EAX |= 0x005f;
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X86_ECX &= 0xffffff00;
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X86_ECX |= 0x00; /* Use video bios default */
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X86_ECX |= 0x00; /* Use video BIOS default */
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res = 1;
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break;
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case 0x5f35:
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X86_EAX &= 0xffff0000;
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X86_EAX |= 0x005f;
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X86_ECX &= 0xffff0000;
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X86_ECX |= 0x0000; /* Use video bios default */
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X86_ECX |= 0x0000; /* Use video BIOS default */
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res = 1;
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break;
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case 0x5f51:
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@ -48,7 +48,7 @@ static void hybrid_graphics_init(void)
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pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
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}
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// OC3 set in bios to port 2-7, OC7 set in bios to port 10-13
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// OC3 set in BIOS to port 2-7, OC7 set in BIOS to port 10-13
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const struct southbridge_usb_port mainboard_usb_ports[] = {
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{ 1, 1, 0 }, /* P0: system port 4, OC0 */
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{ 1, 1, 1 }, /* P1: system port 2 (EHCI debug), OC 1 */
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@ -733,7 +733,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
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/* Enable Audio clk gate and power gate */
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silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable;
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silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable;
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/* Bios config lockdown Audio clk and power gate */
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/* BIOS config lockdown Audio clk and power gate */
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silconfig->BiosCfgLockDown = cfg->hdaudio_bios_config_lockdown;
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if (CONFIG(SOC_INTEL_GLK))
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glk_fsp_silicon_init_params_cb(cfg, silconfig);
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@ -237,7 +237,7 @@ void fast_spi_cache_bios_region(void)
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/* LOCAL APIC default address is 0xFEE0000, bios_size over 16MB will
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* cause memory type conflict when setting memory type to write
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* protection, so limit the cached bios region to be no more than 16MB.
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* protection, so limit the cached BIOS region to be no more than 16MB.
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* */
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bios_size = MIN(bios_size, 16 * MiB);
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if (bios_size <= 0)
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@ -69,12 +69,12 @@ static void fast_spi_lockdown_cfg(int chipset_lockdown)
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/* Lock FAST_SPIBAR */
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fast_spi_lock_bar();
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/* Set Bios Interface Lock, Bios Lock */
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/* Set BIOS Interface Lock, BIOS Lock */
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if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
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/* Bios Interface Lock */
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/* BIOS Interface Lock */
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fast_spi_set_bios_interface_lock_down();
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/* Bios Lock */
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/* BIOS Lock */
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fast_spi_set_lock_enable();
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}
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}
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@ -22,7 +22,7 @@
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static void lpc_lockdown_config(int chipset_lockdown)
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{
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/* Set Bios Interface Lock, Bios Lock */
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/* Set BIOS Interface Lock, BIOS Lock */
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if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
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lpc_set_bios_interface_lock_down();
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lpc_set_lock_enable();
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@ -32,7 +32,7 @@ Show only GPIO register differences from hardware defaults.
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Dump I/O Controller Hub (ICH) southbridge RCBA registers.
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.TP
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.B "\-s, \-\-spi"
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Dump I/O Controller Hub (ICH) southbridge SPI registers and bios control.
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Dump I/O Controller Hub (ICH) southbridge SPI registers and BIOS control.
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.TP
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.B "\-f, \-\-gfx"
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.RB "Dump graphics registers. " \
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@ -22,7 +22,7 @@ static const io_register_t pch_bios_cntl_registers[] = {
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{ 0x1, 1, "BLE - lock enable" },
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{ 0x2, 2, "SPI Read configuration" },
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{ 0x4, 1, "TopSwapStatus" },
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{ 0x5, 1, "SMM Bios Write Protect Disable" },
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{ 0x5, 1, "SMM BIOS Write Protect Disable" },
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{ 0x6, 2, "reserved" },
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};
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