From 6dcb6c2fa400495df97aa2e95a1897cd4b05a1a8 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Thu, 26 Jul 2018 17:07:13 -0600 Subject: [PATCH] soc/amd/stoneyridge: Add IGFX device ACPI ASL entry Add internal graphics device 00.01.00 to the ACPI tables so that the ACPI PCI option ROM save functions have a proper scope to save the ROM to. BUG=b:111697181 TEST=Check coreboot log doesn't have "PCI: 00:01.0: Missing ACPI scope" and check _ROM method is added in the SSDT1. Change-Id: I2c9ef8d9dff76805b1fcde2ccceef958a5b53b4f Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/27653 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth Reviewed-by: Paul Menzel Reviewed-by: Marshall Dawson --- src/soc/amd/stoneyridge/acpi/northbridge.asl | 5 +++++ src/soc/amd/stoneyridge/chip.c | 2 ++ 2 files changed, 7 insertions(+) diff --git a/src/soc/amd/stoneyridge/acpi/northbridge.asl b/src/soc/amd/stoneyridge/acpi/northbridge.asl index 4df6567e2c..fe78534403 100644 --- a/src/soc/amd/stoneyridge/acpi/northbridge.asl +++ b/src/soc/amd/stoneyridge/acpi/northbridge.asl @@ -46,6 +46,11 @@ Device(AMRT) { Name(_ADR, 0x00000000) } /* end AMRT */ +/* Internal Graphics */ +Device(IGFX) { + Name(_ADR, 0x00010000) +} + /* Gpp 0 */ Device(PBR4) { Name(_ADR, 0x00020001) diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 9ca2db7e85..33c17308c8 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -82,6 +82,8 @@ const char *soc_acpi_name(const struct device *dev) return NULL; switch (dev->path.pci.devfn) { + case GFX_DEVFN: + return "IGFX"; case PCIE0_DEVFN: return "PBR4"; case PCIE1_DEVFN: