soc/skylake/cpu: Fix Intel SpeedStep enable/disable

In an attempt at consolidation, commit 0a203d1 [1] introduced
an additional read/write of the MISC_ENABLE msr, as well a bug
which nullified the setting of Intel SpeedStep by inserting said
read/write calls in between another set of read/write calls to the
same msr.  Fix by reverting to previous (simpler) implementation.

[1] soc/intel/skylake: Use CPU common library code
https://review.coreboot.org/19566

Test: boot Linux on Librem13v2, read MISC_ENABLE msr and verify
SpeedStep bit correctly set based on devicetree setting.

Change-Id: Id2ac660bf8ea56d45e8c3f631a586b74106a6cc9
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/25330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/skylake/cpu.c

@@ -293,9 +293,9 @@ static void configure_misc(void)
 	msr.lo |= (1 << 0);	/* Fast String enable */
 	msr.lo |= (1 << 3);	/* TM1/TM2/EMTTM enable */
 	if (conf->eist_enable)
-		cpu_enable_eist();
+		msr.lo |= (1 << 16);	/* Enhanced SpeedStep Enable */
 	else
-		cpu_disable_eist();
+		msr.lo &= ~(1 << 16);	/* Enhanced SpeedStep Disable */
 	wrmsr(IA32_MISC_ENABLE, msr);
 
 	/* Disable Thermal interrupts */