From 6dd6c6850785dc55854446503dd2fe851fc6a77e Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Thu, 2 Oct 2003 00:08:42 +0000 Subject: [PATCH] IRQ setup for EPIA git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1174 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/devices/pci_device.c | 66 +++++++++++++++++++++++++++++ src/southbridge/via/vt8231/vt8231.c | 61 +++++++++++++++++++++++++- 2 files changed, 126 insertions(+), 1 deletion(-) diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c index a4789d22f4..a91381f0d6 100644 --- a/src/devices/pci_device.c +++ b/src/devices/pci_device.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -679,3 +680,68 @@ unsigned int pci_scan_bridge(struct device *dev, unsigned int max) printk_spew("%s returns max %d\n", __FUNCTION__, max); return max; } +/* + Tell the EISA int controller this int must be level triggered + THIS IS A KLUDGE -- sorry, this needs to get cleaned up. +*/ +static void pci_level_irq(unsigned char intNum) +{ + unsigned intBits = inb(0x4d0) | (((unsigned) inb(0x4d1)) << 8); + + intBits |= (1 << intNum); + + // Write new values + outb((unsigned char) intBits, 0x4d0); + outb((unsigned char) (intBits >> 8), 0x4d1); +} + + +/* + This function assigns IRQs for all functions contained within + the indicated device address. If the device does not exist or does + not require interrupts then this function has no effect. + + This function should be called for each PCI slot in your system. + + pIntAtoD is an array of IRQ #s that are assigned to PINTA through PINTD of + this slot. + The particular irq #s that are passed in depend on the routing inside + your southbridge and on your motherboard. + + -kevinh@ispiri.com +*/ +void pci_assign_irqs(unsigned bus, unsigned slot, + const unsigned char pIntAtoD[4]) +{ + unsigned functNum; + device_t pdev; + unsigned char line; + unsigned char irq; + unsigned char readback; + + /* Each slot may contain up to eight functions */ + for (functNum = 0; functNum < 8; functNum++) { + pdev = dev_find_slot(bus, (slot << 3) + functNum); + + if (pdev) { + line = pci_read_config8(pdev, PCI_INTERRUPT_PIN); + + // PCI spec says all other values are reserved + if ((line >= 1) && (line <= 4)) { + irq = pIntAtoD[line - 1]; + + printk_debug("Assigning IRQ %d to %d:%x.%d\n", \ + irq, bus, slot, functNum); + + pci_write_config8(pdev, PCI_INTERRUPT_LINE,\ + pIntAtoD[line - 1]); + + readback = pci_read_config8(pdev, PCI_INTERRUPT_LINE); + printk_debug(" Readback = %d\n", readback); + + // Change to level triggered + pci_level_irq(pIntAtoD[line - 1]); + } + } + } +} diff --git a/src/southbridge/via/vt8231/vt8231.c b/src/southbridge/via/vt8231/vt8231.c index 95e2ca573a..e849be16ac 100644 --- a/src/southbridge/via/vt8231/vt8231.c +++ b/src/southbridge/via/vt8231/vt8231.c @@ -146,12 +146,64 @@ static void ethernet_fixup() * in the C code. */ static void vt8231_pci_enable(struct southbridge_via_vt8231_config *conf) { + /* unsigned long busdevfn = 0x8000; if (conf->enable_ide) { printk_spew("%s: enabling IDE function\n", __FUNCTION__); } - + */ } + +/* PIRQ init + */ +void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char pIntAtoD[4]); + + +static const unsigned char southbridgeIrqs[4] = { 11, 5, 10, 12 }; +static const unsigned char enetIrqs[4] = { 11, 5, 10, 12 }; +static const unsigned char slotIrqs[4] = { 5, 10, 12, 11 }; + +/* + Our IDSEL mappings are as follows + PCI slot is AD31 (device 15) (00:14.0) + Southbridge is AD28 (device 12) (00:11.0) +*/ +static void pci_routing_fixup(void) +{ + device_t dev; + + dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0); + printk_info("%s: dev is %p\n", __FUNCTION__, dev); + if (dev) { + /* initialize PCI interupts - these assignments depend + on the PCB routing of PINTA-D + + PINTA = IRQ11 + PINTB = IRQ5 + PINTC = IRQ10 + PINTD = IRQ12 + */ + pci_write_config8(dev, 0x55, 0xb0); + pci_write_config8(dev, 0x56, 0xa5); + pci_write_config8(dev, 0x57, 0xc0); + } + + // Standard southbridge components + printk_info("setting southbridge\n"); + pci_assign_irqs(0, 0x11, southbridgeIrqs); + + // Ethernet built into southbridge + printk_info("setting ethernet\n"); + pci_assign_irqs(0, 0x12, enetIrqs); + + // PCI slot + printk_info("setting pci slot\n"); + pci_assign_irqs(0, 0x14, slotIrqs); + printk_info("%s: DONE\n", __FUNCTION__); +} + + + static void vt8231_init(struct southbridge_via_vt8231_config *conf) { unsigned char enables; @@ -377,6 +429,13 @@ southbridge_init(struct chip *chip, enum chip_pass pass) case CONF_PASS_POST_PCI: vt8231_init(conf); + printk_err("FUCK! ROUTING FIXUP!\n"); + pci_routing_fixup(); + + break; + case CONF_PASS_PRE_BOOT: + printk_err("FUCK! ROUTING FIXUP!\n"); + pci_routing_fixup(); break; default: