GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mainboard/google/fizz: Enable S0ix 

Enable S0ix for fizz.

BUG=b:67598361
BRANCH=None
TEST=None.  Need to be tested with EC and kernel as well.

Change-Id: I981d2cc7e969a44567b0f21f63f68c78e73f5cb5
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/22955
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Shelley Chen 2017-12-20 10:43:25 -08:00 committed by Shelley Chen
parent ceeafa45ca
commit 6dd9e5983e
1 changed files with 3 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/mainboard/google/fizz/devicetree.cb
View File

@ -50,6 +50,9 @@ chip soc/intel/skylake
# Enable DPTF # Enable DPTF
register "dptf_enable" = "1" register "dptf_enable" = "1"
# Enable S0ix
register "s0ix_enable" = "1"
# FSP Configuration # FSP Configuration
register "ProbelessTrace" = "0" register "ProbelessTrace" = "0"
register "EnableLan" = "1" register "EnableLan" = "1"