GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

src/superio: Fix typo and remove unneeded whitespace 

Change-Id: Iadc28d1632aa9b7d0b028c229049a348d5c07882
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Elyes HAOUAS 2018-08-07 12:12:58 +02:00 committed by Martin Roth
parent 089b685761
commit 6de6571f1c
3 changed files with 15 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/superio/ite/it8772f/it8772f.h
View File

@ -120,7 +120,7 @@ enum thermal_mode {
/* GPIO Inernal Pull-up: 1: Enable, 0: Disable */
#define GPIO_REG_PULLUP(x) (0xb8 + (x))
/* GPIO Fucntion Select: 1: Simple I/O, 0: Alternate function */
/* GPIO Function Select: 1: Simple I/O, 0: Alternate function */
#define GPIO_REG_ENABLE(x) (0xc0 + (x))
/* GPIO Mode: 0: input mode, 1: output mode */

2
src/superio/smsc/sio1036/sio1036.h
View File

@ -20,7 +20,7 @@
#define UART_POWER_DOWN (1 << 7)
#define LPT_POWER_DOWN (1 << 2)
#define IR_OUPUT_MUX (1 << 6)
#define IR_OUTPUT_MUX (1 << 6)
#include <arch/io.h>
#include <stdint.h>

26
src/superio/smsc/sio1036/sio1036_early_init.c
View File

@ -38,8 +38,8 @@ static u8 detect_sio1036_chip(unsigned port)
pnp_devfn_t dev = PNP_DEV(port, SIO1036_SP1);
unsigned data;
sio1036_enter_conf_state (dev);
data = pnp_read_config (dev, 0x0D);
sio1036_enter_conf_state(dev);
data = pnp_read_config(dev, 0x0D);
sio1036_exit_conf_state(dev);
/* Detect SMSC SIO1036 chip */
@ -59,37 +59,37 @@ void sio1036_enable_serial(pnp_devfn_t dev, u16 iobase)
if (detect_sio1036_chip(port) != 0)
return;
sio1036_enter_conf_state (dev);
sio1036_enter_conf_state(dev);
/* Enable SMSC UART 0 */
/* Valid configuration cycle */
pnp_write_config (dev, 0x00, 0x28);
pnp_write_config(dev, 0x00, 0x28);
/* PP power/mode/cr lock */
pnp_write_config (dev, 0x01, 0x98 | LPT_POWER_DOWN);
pnp_write_config (dev, 0x02, 0x08 | UART_POWER_DOWN);
pnp_write_config(dev, 0x01, 0x98 | LPT_POWER_DOWN);
pnp_write_config(dev, 0x02, 0x08 | UART_POWER_DOWN);
/*Auto power management*/
pnp_write_config (dev, 0x07, 0x00 );
pnp_write_config(dev, 0x07, 0x00);
/*ECP FIFO threhod */
pnp_write_config (dev, 0x0A, 0x00 | IR_OUPUT_MUX);
pnp_write_config(dev, 0x0A, 0x00 | IR_OUTPUT_MUX);
/*GPIO direction register 2 */
pnp_write_config (dev, 0x033, 0x00);
pnp_write_config(dev, 0x033, 0x00);
/*UART Mode */
pnp_write_config (dev, 0x0C, 0x02);
pnp_write_config(dev, 0x0C, 0x02);
/* GPIO polarity regisgter 2 */
pnp_write_config (dev, 0x034, 0x00);
pnp_write_config(dev, 0x034, 0x00);
/* Enable SMSC UART 0 */
/*Set base io address */
pnp_write_config (dev, 0x25, (u8)(iobase >> 2));
pnp_write_config(dev, 0x25, (u8)(iobase >> 2));
/* Set UART IRQ onto 0x04 */
pnp_write_config (dev, 0x28, 0x04);
pnp_write_config(dev, 0x28, 0x04);
sio1036_exit_conf_state(dev);
}