mb/google/volteer/var/voema: Update Aux settings for Port 0
On Voema port 0 (MB PORT) does not have a retimer so the port needs to be configured for the SOC to handle Aux orientation flipping. BUG=b:176462544 TEST=tested on voema Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I3d31a5b848f56126f8ffe2babb29085471e8224f Reviewed-on: https://review.coreboot.org/c/coreboot/+/48976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
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@ -5,6 +5,10 @@ chip soc/intel/tigerlake
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# and controller 1 channel 0 and 1.
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# and controller 1 channel 0 and 1.
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register "CmdMirror" = "0x00000033"
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register "CmdMirror" = "0x00000033"
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register "TcssAuxOri" = "1"
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register "IomTypeCPortPadCfg[0]" = "0x090E000A"
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register "IomTypeCPortPadCfg[1]" = "0x090E000D"
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# Disable WLAN PCIE 7
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# Disable WLAN PCIE 7
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register "PcieRpEnable[6]" = "0"
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register "PcieRpEnable[6]" = "0"
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register "PcieRpLtrEnable[6]" = "0"
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register "PcieRpLtrEnable[6]" = "0"
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@ -105,8 +109,6 @@ chip soc/intel/tigerlake
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chip drivers/intel/pmc_mux/conn
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chip drivers/intel/pmc_mux/conn
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register "usb2_port_number" = "5"
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register "usb2_port_number" = "5"
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register "usb3_port_number" = "1"
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register "usb3_port_number" = "1"
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# SBU is fixed, HSL follows CC
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register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
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device generic 0 alias conn0 on end
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device generic 0 alias conn0 on end
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end
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end
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chip drivers/intel/pmc_mux/conn
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chip drivers/intel/pmc_mux/conn
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