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src: Remove duplicated round up function 

This removes CEIL_DIV and div_round_up() altogether and
replace it by DIV_ROUND_UP defined in commonlib/helpers.h.

Change-Id: I9aabc3fbe7834834c92d6ba59ff0005986622a34
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Elyes HAOUAS 2018-11-26 22:53:49 +01:00 committed by Patrick Georgi
parent 1a5ce95815
commit 6df3b64c77
29 changed files with 79 additions and 89 deletions
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6
src/arch/arm/armv7/mmu.c
View File

@ -236,7 +236,7 @@ void mmu_disable_range_kb(u32 start_kb, u32 size_kb)
printk(BIOS_DEBUG, "Setting address range [%#.8x:%#.8x) as unmapped\n",
start_kb * KiB, (start_kb + size_kb) * KiB);
mmu_fill_table(table, (start_kb & mask) / (PAGE_SIZE/KiB),
div_round_up((start_kb + size_kb) & mask, PAGE_SIZE/KiB),
DIV_ROUND_UP((start_kb + size_kb) & mask, PAGE_SIZE/KiB),
(start_kb & ~mask) * KiB, PAGE_SHIFT, 0);
}
@ -246,7 +246,7 @@ void mmu_disable_range(u32 start_mb, u32 size_mb)
start_mb * MiB, (start_mb + size_mb) * MiB);
assert(start_mb + size_mb <= 4 * (GiB/MiB));
mmu_fill_table(ttb_buff, start_mb / (BLOCK_SIZE/MiB),
div_round_up(start_mb + size_mb, BLOCK_SIZE/MiB),
DIV_ROUND_UP(start_mb + size_mb, BLOCK_SIZE/MiB),
0, BLOCK_SHIFT, 0);
}
@ -256,7 +256,7 @@ void mmu_config_range(u32 start_mb, u32 size_mb, enum dcache_policy policy)
start_mb * MiB, (start_mb + size_mb) * MiB, attrs[policy].name);
assert(start_mb + size_mb <= 4 * (GiB/MiB));
mmu_fill_table(ttb_buff, start_mb / (BLOCK_SIZE/MiB),
div_round_up(start_mb + size_mb, BLOCK_SIZE/MiB),
DIV_ROUND_UP(start_mb + size_mb, BLOCK_SIZE/MiB),
0, BLOCK_SHIFT, ATTR_BLOCK | attrs[policy].value);
}

1
src/commonlib/include/commonlib/helpers.h
View File

@ -36,7 +36,6 @@
#define MAX(a, b) ((a) > (b) ? (a) : (b))
#endif
#define ABS(a) (((a) < 0) ? (-(a)) : (a))
#define CEIL_DIV(a, b) (((a) + (b) - 1) / (b))
#define IS_POWER_OF_2(x) (((x) & ((x) - 1)) == 0)
#define DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y))
/*

6
src/cpu/allwinner/a10/clock.c
View File

@ -247,9 +247,9 @@ void a1x_set_cpu_clock(u16 cpu_clk_mhz)
* will always be in spec, as long as AHB is in spec, although the max
* AHB0 clock we can get is 125 MHz
*/
axi = CEIL_DIV(actual_mhz, 450); /* Max 450 MHz */
ahb = CEIL_DIV(actual_mhz/axi, 250); /* Max 250 MHz */
apb0 = 2; /* Max 150 MHz */
axi = DIV_ROUND_UP(actual_mhz, 450); /* Max 450 MHz */
ahb = DIV_ROUND_UP(actual_mhz/axi, 250); /* Max 250 MHz */
apb0 = 2; /* Max 150 MHz */
ahb_exp = log2_ceil(ahb);
ahb = 1 << ahb_exp;

2
src/cpu/x86/tsc/delay_tsc.c
View File

@ -83,7 +83,7 @@ static unsigned long calibrate_tsc_with_pit(void)
if (end.lo <= CALIBRATE_DIVISOR)
goto bad_ctc;
return CEIL_DIV(end.lo, CALIBRATE_DIVISOR);
return DIV_ROUND_UP(end.lo, CALIBRATE_DIVISOR);
}
/*

8
src/include/stdlib.h
View File

@ -11,12 +11,4 @@ void *malloc(size_t size);
/* We never free memory */
static inline void free(void *ptr) {}
#ifndef __ROMCC__
static inline unsigned long div_round_up(unsigned int n, unsigned int d)
{
return (n + d - 1) / d;
}
#endif
#endif /* STDLIB_H */

2
src/lib/edid.c
View File

@ -1689,7 +1689,7 @@ void edid_set_framebuffer_bits_per_pixel(struct edid *edid, int fb_bpp,
edid->framebuffer_bits_per_pixel = fb_bpp;
edid->bytes_per_line = ALIGN_UP(edid->mode.ha *
div_round_up(fb_bpp, 8), row_byte_alignment);
DIV_ROUND_UP(fb_bpp, 8), row_byte_alignment);
edid->x_resolution = edid->bytes_per_line / (fb_bpp / 8);
edid->y_resolution = edid->mode.va;
}

2
src/mainboard/google/nyan/romstage.c
View File

@ -55,7 +55,7 @@ static void __attribute__((noinline)) romstage(void)
/* Device memory below DRAM is uncached. */
mmu_config_range(0, dram_start_mb, DCACHE_OFF);
/* SRAM is cached. MMU code will round size up to page size. */
mmu_config_range((uintptr_t)_sram/MiB, div_round_up(_sram_size, MiB),
mmu_config_range((uintptr_t)_sram/MiB, DIV_ROUND_UP(_sram_size, MiB),
DCACHE_WRITEBACK);
/* DRAM is cached. */
mmu_config_range(dram_start_mb, dram_size_mb, DCACHE_WRITEBACK);

2
src/mainboard/google/nyan_big/romstage.c
View File

@ -55,7 +55,7 @@ static void __attribute__((noinline)) romstage(void)
/* Device memory below DRAM is uncached. */
mmu_config_range(0, dram_start_mb, DCACHE_OFF);
/* SRAM is cached. MMU code will round size up to page size. */
mmu_config_range((uintptr_t)_sram/MiB, div_round_up(_sram_size, MiB),
mmu_config_range((uintptr_t)_sram/MiB, DIV_ROUND_UP(_sram_size, MiB),
DCACHE_WRITEBACK);
/* DRAM is cached. */
mmu_config_range(dram_start_mb, dram_size_mb, DCACHE_WRITEBACK);

2
src/mainboard/google/nyan_blaze/romstage.c
View File

@ -57,7 +57,7 @@ static void __attribute__((noinline)) romstage(void)
/* Device memory below DRAM is uncached. */
mmu_config_range(0, dram_start_mb, DCACHE_OFF);
/* SRAM is cached. MMU code will round size up to page size. */
mmu_config_range((uintptr_t)_sram/MiB, div_round_up(_sram_size, MiB),
mmu_config_range((uintptr_t)_sram/MiB, DIV_ROUND_UP(_sram_size, MiB),
DCACHE_WRITEBACK);
/* The space above DRAM is uncached. */
if (dram_end_mb < 4096)

12
src/northbridge/intel/gm45/raminit.c
View File

@ -361,8 +361,6 @@ static void collect_ddr3(sysinfo_t *const sysinfo, spdinfo_t *const config)
}
}
#define ROUNDUP_DIV(val, by) CEIL_DIV(val, by)
#define ROUNDUP_DIV_THIS(val, by) val = ROUNDUP_DIV(val, by)
static fsb_clock_t read_fsb_clock(void)
{
switch (MCHBAR32(CLKCFG_MCHBAR) & CLKCFG_FSBCLK_MASK) {
@ -452,7 +450,7 @@ static unsigned int find_common_clock_cas(sysinfo_t *const sysinfo,
if (!clock)
die("Couldn't find compatible clock / CAS settings.\n");
tCKproposed = 8000 / clock;
CAS = ROUNDUP_DIV(tAAmin, tCKproposed);
CAS = DIV_ROUND_UP(tAAmin, tCKproposed);
printk(BIOS_SPEW, "Trying CAS %u, tCK %u.\n", CAS, tCKproposed);
for (; CAS <= DDR3_MAX_CAS; ++CAS)
if (cas_latencies & (1 << CAS))
@ -488,10 +486,10 @@ static void calculate_derived_timings(sysinfo_t *const sysinfo,
if (spdinfo->channel[i].tWR > tWRmin)
tWRmin = spdinfo->channel[i].tWR;
}
ROUNDUP_DIV_THIS(tRASmin, tCLK);
ROUNDUP_DIV_THIS(tRPmin, tCLK);
ROUNDUP_DIV_THIS(tRCDmin, tCLK);
ROUNDUP_DIV_THIS(tWRmin, tCLK);
tRASmin = DIV_ROUND_UP(tRASmin, tCLK);
tRPmin = DIV_ROUND_UP(tRPmin, tCLK);
tRCDmin = DIV_ROUND_UP(tRCDmin, tCLK);
tWRmin = DIV_ROUND_UP(tWRmin, tCLK);
/* Lookup tRFC and calculate common tRFCmin. */
const unsigned int tRFC_from_clock_and_cap[][4] = {

4
src/northbridge/intel/nehalem/raminit.c
View File

@ -602,7 +602,7 @@ static void calculate_timings(struct raminfo *info)
break;
}
}
min_cas_latency = CEIL_DIV(cas_latency_time, cycletime);
min_cas_latency = DIV_ROUND_UP(cas_latency_time, cycletime);
cas_latency = 0;
while (supported_cas_latencies) {
cas_latency = find_highest_bit_set(supported_cas_latencies) + 3;
@ -3231,7 +3231,7 @@ static unsigned gcd(unsigned a, unsigned b)
static inline int div_roundup(int a, int b)
{
return CEIL_DIV(a, b);
return DIV_ROUND_UP(a, b);
}
static unsigned lcm(unsigned a, unsigned b)

22
src/northbridge/via/vx900/raminit_ddr3.c
View File

@ -572,7 +572,7 @@ static void vx900_dram_timing(ramctr_timing * ctrl)
printram("Selected DRAM frequency: %u MHz\n", val32);
/* Find CAS and CWL latencies */
val = CEIL_DIV(ctrl->tAA, ctrl->tCK);
val = DIV_ROUND_UP(ctrl->tAA, ctrl->tCK);
printram("Minimum CAS latency : %uT\n", val);
/* Find lowest supported CAS latency that satisfies the minimum value */
while (!((ctrl->cas_supported >> (val - 4)) & 1)
@ -591,30 +591,30 @@ static void vx900_dram_timing(ramctr_timing * ctrl)
pci_write_config8(MCU, 0xc0, reg8);
/* Find tRCD */
val = CEIL_DIV(ctrl->tRCD, ctrl->tCK);
val = DIV_ROUND_UP(ctrl->tRCD, ctrl->tCK);
printram("Selected tRCD : %uT\n", val);
reg8 = ((val - 4) & 0x7) << 4;
/* Find tRP */
val = CEIL_DIV(ctrl->tRP, ctrl->tCK);
val = DIV_ROUND_UP(ctrl->tRP, ctrl->tCK);
printram("Selected tRP : %uT\n", val);
reg8 |= ((val - 4) & 0x7);
pci_write_config8(MCU, 0xc1, reg8);
/* Find tRAS */
val = CEIL_DIV(ctrl->tRAS, ctrl->tCK);
val = DIV_ROUND_UP(ctrl->tRAS, ctrl->tCK);
printram("Selected tRAS : %uT\n", val);
reg8 = ((val - 15) & 0x7) << 4;
/* Find tWR */
ctrl->WR = CEIL_DIV(ctrl->tWR, ctrl->tCK);
ctrl->WR = DIV_ROUND_UP(ctrl->tWR, ctrl->tCK);
printram("Selected tWR : %uT\n", ctrl->WR);
reg8 |= ((ctrl->WR - 4) & 0x7);
pci_write_config8(MCU, 0xc2, reg8);
/* Find tFAW */
tFAW = CEIL_DIV(ctrl->tFAW, ctrl->tCK);
tFAW = DIV_ROUND_UP(ctrl->tFAW, ctrl->tCK);
printram("Selected tFAW : %uT\n", tFAW);
/* Find tRRD */
tRRD = CEIL_DIV(ctrl->tRRD, ctrl->tCK);
tRRD = DIV_ROUND_UP(ctrl->tRRD, ctrl->tCK);
printram("Selected tRRD : %uT\n", tRRD);
val = tFAW - 4 * tRRD; /* number of cycles above 4*tRRD */
reg8 = ((val - 0) & 0x7) << 4;
@ -622,11 +622,11 @@ static void vx900_dram_timing(ramctr_timing * ctrl)
pci_write_config8(MCU, 0xc3, reg8);
/* Find tRTP */
val = CEIL_DIV(ctrl->tRTP, ctrl->tCK);
val = DIV_ROUND_UP(ctrl->tRTP, ctrl->tCK);
printram("Selected tRTP : %uT\n", val);
reg8 = ((val & 0x3) << 4);
/* Find tWTR */
val = CEIL_DIV(ctrl->tWTR, ctrl->tCK);
val = DIV_ROUND_UP(ctrl->tWTR, ctrl->tCK);
printram("Selected tWTR : %uT\n", val);
reg8 |= ((val - 2) & 0x7);
pci_mod_config8(MCU, 0xc4, 0x3f, reg8);
@ -639,7 +639,7 @@ static void vx900_dram_timing(ramctr_timing * ctrl)
* Since we previously set RxC4[7]
*/
reg8 = pci_read_config8(MCU, 0xc5);
val = CEIL_DIV(ctrl->tRFC, ctrl->tCK);
val = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK);
printram("Minimum tRFC : %uT\n", val);
if (val < 30) {
val = 0;
@ -652,7 +652,7 @@ static void vx900_dram_timing(ramctr_timing * ctrl)
pci_write_config8(MCU, 0xc5, reg8);
/* Where does this go??? */
val = CEIL_DIV(ctrl->tRC, ctrl->tCK);
val = DIV_ROUND_UP(ctrl->tRC, ctrl->tCK);
printram("Required tRC : %uT\n", val);
}

6
src/soc/mediatek/common/spi.c
View File

@ -62,11 +62,11 @@ void mtk_spi_init(unsigned int bus, enum spi_pad_mask pad_select,
struct mtk_spi_regs *regs = slave->regs;
if (speed_hz < SPI_HZ / 2)
div = div_round_up(SPI_HZ, speed_hz);
div = DIV_ROUND_UP(SPI_HZ, speed_hz);
else
div = 1;
sck_ticks = div_round_up(div, 2);
sck_ticks = DIV_ROUND_UP(div, 2);
cs_ticks = sck_ticks * 2;
printk(BIOS_DEBUG, "SPI%u(PAD%u) initialized at %u Hz\n",
@ -153,7 +153,7 @@ static int do_transfer(const struct spi_slave *slave, void *in, const void *out,
* therefore we need arbitrary data on MOSI which the slave
* must ignore.
*/
uint32_t word_count = div_round_up(size, sizeof(u32));
uint32_t word_count = DIV_ROUND_UP(size, sizeof(u32));
for (i = 0; i < word_count; i++)
write32(&regs->spi_tx_data_reg, MTK_ARBITRARY_VALUE);
}

8
src/soc/mediatek/mt8173/dsi.c
View File

@ -216,11 +216,11 @@ static void mtk_dsi_phy_timconfig(u32 data_rate)
timcon0 = (8 << 24) | (0xa << 16) | (0x6 << 8) | lpx;
timcon1 = (7 << 24) | (5 * lpx << 16) | ((3 * lpx) / 2) << 8 |
(4 * lpx);
timcon2 = ((div_round_up(0x64, cycle_time) + 0xa) << 24) |
(div_round_up(0x150, cycle_time) << 16);
timcon2 = ((DIV_ROUND_UP(0x64, cycle_time) + 0xa) << 24) |
(DIV_ROUND_UP(0x150, cycle_time) << 16);
timcon3 = (2 * lpx) << 16 |
div_round_up(80 + 52 * ui, cycle_time) << 8 |
div_round_up(0x40, cycle_time);
DIV_ROUND_UP(80 + 52 * ui, cycle_time) << 8 |
DIV_ROUND_UP(0x40, cycle_time);
dsi_write32(&dsi0->dsi_phy_timecon0, timcon0);
dsi_write32(&dsi0->dsi_phy_timecon1, timcon1);

2
src/soc/mediatek/mt8173/i2c.c
View File

@ -98,7 +98,7 @@ void mtk_i2c_bus_init(uint8_t bus)
/* Calculate i2c frequency */
sample_div = 1;
step_div = div_round_up(I2C_CLK_HZ, (400 * KHz * sample_div * 2));
step_div = DIV_ROUND_UP(I2C_CLK_HZ, (400 * KHz * sample_div * 2));
i2c_freq = I2C_CLK_HZ / (step_div * sample_div * 2);
assert(sample_div < 8 && step_div < 64 && i2c_freq < 400 * KHz &&
i2c_freq >= 380 * KHz);

8
src/soc/nvidia/tegra124/clock.c
View File

@ -247,17 +247,17 @@ static void init_utmip_pll(void)
1 << 8); /* (rst) phy_divm */
write32(&clk_rst->utmip_pll_cfg1,
CEIL_DIV(khz, 8000) << 27 | /* pllu_enbl_cnt / 8 (1us) */
DIV_ROUND_UP(khz, 8000) << 27 | /* pllu_enbl_cnt / 8 (1us) */
0 << 16 | /* PLLU pwrdn */
0 << 14 | /* pll_enable pwrdn */
0 << 12 | /* pll_active pwrdn */
CEIL_DIV(khz, 102) << 0); /* phy_stbl_cnt / 256 (2.5ms) */
DIV_ROUND_UP(khz, 102) << 0); /* phy_stbl_cnt / 256 (2.5ms) */
/* TODO: TRM can't decide if actv is 5us or 10us, keep an eye on it */
write32(&clk_rst->utmip_pll_cfg2,
0 << 24 | /* SAMP_D/XDEV pwrdn */
CEIL_DIV(khz, 3200) << 18 | /* phy_actv_cnt / 16 (5us) */
CEIL_DIV(khz, 256) << 6 | /* pllu_stbl_cnt / 256 (1ms) */
DIV_ROUND_UP(khz, 3200) << 18 | /* phy_actv_cnt / 16 (5us) */
DIV_ROUND_UP(khz, 256) << 6 | /* pllu_stbl_cnt / 256 (1ms) */
0 << 4 | /* SAMP_C/USB3 pwrdn */
0 << 2 | /* SAMP_B/XHOST pwrdn */
0 << 0); /* SAMP_A/USBD pwrdn */

4
src/soc/nvidia/tegra124/include/soc/clock.h
View File

@ -200,7 +200,7 @@ enum {
* and voila, upper 7 bits are (ref/freq-1), and lowest bit is h. Since you
* will assign this to a u8, it gets nicely truncated for you.
*/
#define CLK_DIVIDER(REF, FREQ) (div_round_up(((REF) * 2), (FREQ)) - 2)
#define CLK_DIVIDER(REF, FREQ) (DIV_ROUND_UP(((REF) * 2), (FREQ)) - 2)
/* Calculate clock frequency value from reference and clock divider value
* The discussion in the book is pretty lacking.
@ -253,7 +253,7 @@ static inline void _clock_set_div(u32 *reg, const char *name, u32 div,
*/
#define clock_configure_i2c_scl_freq(device, src, freq) \
_clock_set_div(&clk_rst->clk_src_##device, #device, \
div_round_up(TEGRA_##src##_KHZ, (freq) * (0x19 + 1) * 8) - 1, \
DIV_ROUND_UP(TEGRA_##src##_KHZ, (freq) * (0x19 + 1) * 8) - 1, \
0xffff, src)
enum clock_source { /* Careful: Not true for all sources, always check TRM! */

2
src/soc/nvidia/tegra124/verstage.c
View File

@ -30,7 +30,7 @@ static void enable_cache(void)
/* Whole space is uncached. */
mmu_config_range(0, 4096, DCACHE_OFF);
/* SRAM is cached. MMU code will round size up to page size. */
mmu_config_range((uintptr_t)_sram/MiB, div_round_up(_sram_size, MiB),
mmu_config_range((uintptr_t)_sram/MiB, DIV_ROUND_UP(_sram_size, MiB),
DCACHE_WRITEBACK);
mmu_disable_range(0, 1);
dcache_mmu_enable();

4
src/soc/nvidia/tegra210/clock.c
View File

@ -330,7 +330,7 @@ static void init_utmip_pll(void)
/* CFG1 */
u32 pllu_enb_ct = 0;
u32 phy_stb_ct = div_round_up(khz, 300); /* phy_stb_ct = 128 */
u32 phy_stb_ct = DIV_ROUND_UP(khz, 300); /* phy_stb_ct = 128 */
write32(CLK_RST_REG(utmip_pll_cfg1),
pllu_enb_ct << UTMIP_CFG1_PLLU_ENABLE_DLY_COUNT_SHIFT |
UTMIP_CFG1_FORCE_PLLU_POWERDOWN_ENABLE |
@ -341,7 +341,7 @@ static void init_utmip_pll(void)
/* CFG2 */
u32 pllu_stb_ct = 0;
u32 phy_act_ct = div_round_up(khz, 6400); /* phy_act_ct = 6 */
u32 phy_act_ct = DIV_ROUND_UP(khz, 6400); /* phy_act_ct = 6 */
write32(CLK_RST_REG(utmip_pll_cfg2),
phy_act_ct << UTMIP_CFG2_PLL_ACTIVE_DLY_COUNT_SHIFT |
pllu_stb_ct << UTMIP_CFG2_PLLU_STABLE_COUNT_SHIFT |

5
src/soc/nvidia/tegra210/include/soc/clock.h
View File

@ -289,7 +289,7 @@ enum {
* and voila, upper 7 bits are (ref/freq-1), and lowest bit is h. Since you
* will assign this to a u8, it gets nicely truncated for you.
*/
#define CLK_DIVIDER(REF, FREQ) (div_round_up(((REF) * 2), (FREQ)) - 2)
#define CLK_DIVIDER(REF, FREQ) (DIV_ROUND_UP(((REF) * 2), (FREQ)) - 2)
/* Calculate clock frequency value from reference and clock divider value
* The discussion in the book is pretty lacking.
@ -324,7 +324,8 @@ static inline void _clock_set_div(u32 *reg, const char *name, u32 div,
src << CLK_SOURCE_SHIFT | div);
}
#define get_i2c_clk_div(src,freq) (div_round_up(src, (freq) * (0x19 + 1) * 8) - 1)
#define get_i2c_clk_div(src, freq) \
(DIV_ROUND_UP(src, (freq) * (0x19 + 1) * 8) - 1)
#define get_clk_div(src,freq) CLK_DIVIDER(src,freq)
#define CLK_DIV_MASK 0xff
#define CLK_DIV_MASK_I2C 0xffff

2
src/soc/rockchip/common/i2c.c
View File

@ -280,7 +280,7 @@ void i2c_init(unsigned int bus, unsigned int hz)
/* SCL Divisor = 8*(CLKDIVL + 1 + CLKDIVH + 1)
SCL = PCLK / SCLK Divisor */
clk_div = div_round_up(i2c_src_clk, hz * 8);
clk_div = DIV_ROUND_UP(i2c_src_clk, hz * 8);
divh = clk_div * 3 / 7 - 1;
divl = clk_div - divh - 2;
i2c_clk = i2c_src_clk / (8 * (divl + 1 + divh + 1));

8
src/soc/rockchip/common/rk808.c
View File

@ -92,13 +92,13 @@ void rk808_configure_ldo(int ldo, int millivolts)
case 4:
case 5:
case 8:
vsel = div_round_up(millivolts, 100) - 18;
vsel = DIV_ROUND_UP(millivolts, 100) - 18;
assert(vsel <= 0x10);
break;
case 3:
case 6:
case 7:
vsel = div_round_up(millivolts, 100) - 8;
vsel = DIV_ROUND_UP(millivolts, 100) - 8;
assert(vsel <= 0x11);
break;
default:
@ -118,12 +118,12 @@ void rk808_configure_buck(int buck, int millivolts)
case 1:
case 2:
/* 25mV steps. base = 29 * 25mV = 725 */
vsel = (div_round_up(millivolts, 25) - 29) * 2 + 1;
vsel = (DIV_ROUND_UP(millivolts, 25) - 29) * 2 + 1;
assert(vsel <= 0x3f);
buck_reg = BUCK1SEL + 4 * (buck - 1);
break;
case 4:
vsel = div_round_up(millivolts, 100) - 18;
vsel = DIV_ROUND_UP(millivolts, 100) - 18;
assert(vsel <= 0xf);
buck_reg = BUCK4SEL;
break;

8
src/soc/rockchip/rk3288/clock.c
View File

@ -519,15 +519,15 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div, u32 *ext_div)
return -1;
}
no = div_round_up(VCO_MIN_KHZ, freq_khz);
no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
if (ext_div) {
*ext_div = div_round_up(no, max_no);
no = div_round_up(no, *ext_div);
*ext_div = DIV_ROUND_UP(no, max_no);
no = DIV_ROUND_UP(no, *ext_div);
}
/* only even divisors (and 1) are supported */
if (no > 1)
no = div_round_up(no, 2) * 2;
no = DIV_ROUND_UP(no, 2) * 2;
vco_khz = freq_khz * no;
if (ext_div)

12
src/soc/rockchip/rk3288/sdram.c
View File

@ -644,7 +644,7 @@ static void pctl_cfg(u32 channel,
static void phy_cfg(u32 channel, const struct rk3288_sdram_params *sdram_params)
{
u32 i;
u32 dinit2 = div_round_up(sdram_params->ddr_freq/MHz * 200000, 1000);
u32 dinit2 = DIV_ROUND_UP(sdram_params->ddr_freq/MHz * 200000, 1000);
struct rk3288_ddr_publ_regs *ddr_publ_regs = rk3288_ddr_publ[channel];
struct rk3288_msch_regs *msch_regs = rk3288_msch[channel];
@ -658,14 +658,14 @@ static void phy_cfg(u32 channel, const struct rk3288_sdram_params *sdram_params)
write32(&msch_regs->devtodev,
BUSWRTORD(2) | BUSRDTOWR(2) | BUSRDTORD(1));
write32(&ddr_publ_regs->ptr[0],
PRT_DLLLOCK(div_round_up(sdram_params->ddr_freq / MHz * 5120, 1000))
| PRT_DLLSRST(div_round_up(sdram_params->ddr_freq / MHz * 50, 1000))
PRT_DLLLOCK(DIV_ROUND_UP(sdram_params->ddr_freq / MHz * 5120, 1000))
| PRT_DLLSRST(DIV_ROUND_UP(sdram_params->ddr_freq / MHz * 50, 1000))
| PRT_ITMSRST(8));
write32(&ddr_publ_regs->ptr[1],
PRT_DINIT0(div_round_up(sdram_params->ddr_freq / MHz * 500000, 1000))
| PRT_DINIT1(div_round_up(sdram_params->ddr_freq / MHz * 400, 1000)));
PRT_DINIT0(DIV_ROUND_UP(sdram_params->ddr_freq / MHz * 500000, 1000))
| PRT_DINIT1(DIV_ROUND_UP(sdram_params->ddr_freq / MHz * 400, 1000)));
write32(&ddr_publ_regs->ptr[2], PRT_DINIT2(MIN(dinit2, 0x1ffff))
| PRT_DINIT3(div_round_up(sdram_params->ddr_freq / MHz * 1000, 1000)));
| PRT_DINIT3(DIV_ROUND_UP(sdram_params->ddr_freq / MHz * 1000, 1000)));
switch (sdram_params->dramtype) {
case LPDDR3:

12
src/soc/rockchip/rk3399/clock.c
View File

@ -429,10 +429,10 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div)
return -1;
}
postdiv1 = div_round_up(VCO_MIN_KHZ, freq_khz);
postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
if (postdiv1 > max_postdiv1) {
postdiv2 = div_round_up(postdiv1, max_postdiv1);
postdiv1 = div_round_up(postdiv1, postdiv2);
postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1);
postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2);
}
vco_khz = freq_khz * postdiv1 * postdiv2;
@ -605,9 +605,9 @@ void rkclk_configure_cpu(enum apll_frequencies freq, enum cpu_cluster cluster)
apll_hz = apll_cfgs[freq]->freq;
rkclk_set_pll(pll_con, apll_cfgs[freq]);
aclkm_div = div_round_up(apll_hz, ACLKM_CORE_HZ) - 1;
pclk_dbg_div = div_round_up(apll_hz, PCLK_DBG_HZ) - 1;
atclk_div = div_round_up(apll_hz, ATCLK_CORE_HZ) - 1;
aclkm_div = DIV_ROUND_UP(apll_hz, ACLKM_CORE_HZ) - 1;
pclk_dbg_div = DIV_ROUND_UP(apll_hz, PCLK_DBG_HZ) - 1;
atclk_div = DIV_ROUND_UP(apll_hz, ATCLK_CORE_HZ) - 1;
write32(&cru_ptr->clksel_con[con_base],
RK_CLRSETBITS(ACLKM_CORE_DIV_CON_MASK <<

10
src/soc/rockchip/rk3399/mipi.c
View File

@ -45,7 +45,7 @@ static void rk_mipi_dsi_wait_for_two_frames(struct rk_mipi_dsi *dsi,
int two_frames;
unsigned int refresh = edid->mode.refresh;
two_frames = div_round_up(MSECS_PER_SEC * 2, refresh);
two_frames = DIV_ROUND_UP(MSECS_PER_SEC * 2, refresh);
mdelay(two_frames);
}
@ -158,7 +158,7 @@ static int rk_mipi_dsi_wait_phy_lock(struct rk_mipi_dsi *dsi)
static int rk_mipi_dsi_phy_init(struct rk_mipi_dsi *dsi)
{
int i, vco, val;
int lane_mbps = div_round_up(dsi->lane_bps, USECS_PER_SEC);
int lane_mbps = DIV_ROUND_UP(dsi->lane_bps, USECS_PER_SEC);
struct stopwatch sw;
vco = (lane_mbps < 200) ? 0 : (lane_mbps + 100) / 200;
@ -318,7 +318,7 @@ static int rk_mipi_dsi_get_lane_bps(struct rk_mipi_dsi *dsi,
fref = OSC_HZ;
/* constraint: 5Mhz <= Fref / N <= 40MHz */
min_prediv = div_round_up(fref, 40 * MHz);
min_prediv = DIV_ROUND_UP(fref, 40 * MHz);
max_prediv = fref / (5 * MHz);
/* constraint: 80MHz <= Fvco <= 1500Mhz */
@ -441,7 +441,7 @@ static u32 rk_mipi_dsi_get_hcomponent_lbcc(struct rk_mipi_dsi *dsi,
u64 lbcc_tmp;
lbcc_tmp = hcomponent * dsi->lane_bps / (8 * MSECS_PER_SEC);
lbcc = div_round_up(lbcc_tmp, edid->mode.pixel_clock);
lbcc = DIV_ROUND_UP(lbcc_tmp, edid->mode.pixel_clock);
return lbcc;
}
@ -532,7 +532,7 @@ static void rk_mipi_dsi_init(struct rk_mipi_dsi *dsi)
* which is:
* (lane_mbps >> 3) / 20 > esc_clk_division
*/
u32 esc_clk_division = div_round_up(dsi->lane_bps,
u32 esc_clk_division = DIV_ROUND_UP(dsi->lane_bps,
8 * 20 * USECS_PER_SEC);
write32(&dsi->mipi_regs->dsi_pwr_up, RESET);

2
src/soc/samsung/exynos5250/cpu.c
View File

@ -112,7 +112,7 @@ static void cpu_enable(struct device *dev)
u32 lcdbase = get_fb_base_kb() * KiB;
ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB - FB_SIZE_KB);
mmio_resource(dev, 1, lcdbase / KiB, CEIL_DIV(fb_size, KiB));
mmio_resource(dev, 1, lcdbase / KiB, DIV_ROUND_UP(fb_size, KiB));
exynos_displayport_init(dev, lcdbase, fb_size);

2
src/soc/samsung/exynos5420/clock.c
View File

@ -345,7 +345,7 @@ int clock_set_dwmci(enum periph_id peripheral)
}
printk(BIOS_DEBUG, "%s(%d): sdclkin: %ld\n", __func__, device_index, sdclkin);
cclkin = CEIL_DIV(sdclkin, freq);
cclkin = DIV_ROUND_UP(sdclkin, freq);
set_mmc_clk(device_index, cclkin);
return 0;
}

4
src/soc/samsung/exynos5420/cpu.c
View File

@ -114,7 +114,7 @@ static void exynos_displayport_init(struct device *dev, u32 lcdbase,
dcache_clean_invalidate_by_mva((void *)lower, upper - lower);
mmu_config_range(lower / MiB, (upper - lower) / MiB, DCACHE_OFF);
mmio_resource(dev, 1, lcdbase/KiB, CEIL_DIV(fb_size, KiB));
mmio_resource(dev, 1, lcdbase/KiB, DIV_ROUND_UP(fb_size, KiB));
}
static void tps65090_thru_ec_fet_disable(int index)
@ -134,7 +134,7 @@ static void cpu_enable(struct device *dev)
u32 lcdbase = get_fb_base_kb() * KiB;
ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB - FB_SIZE_KB);
mmio_resource(dev, 1, lcdbase / KiB, CEIL_DIV(fb_size, KiB));
mmio_resource(dev, 1, lcdbase / KiB, DIV_ROUND_UP(fb_size, KiB));
/*
* Disable LCD FETs before we do anything with the display.