mb/google/volteer: Copano: Update SPD table

Add memory table to "mem_list_variant.txt", and command to generate files:
go run ./util/spd_tools/lp4x/gen_part_id.go src/soc/intel/tigerlake/spd src/mainboard/google/volteer/variants/copano/memory/ src/mainboard/google/volteer/variants/copano/memory/mem_list_variant.txt

DRAM Part Name                 ID to assign
MT53D512M64D4NW-046 WT:F       0 (0000)
H9HCNNNCRMBLPR-NEE             0 (0000)
MT53D1G64D4NW-046 WT:A         1 (0001)
H9HCNNNFBMBLPR-NEE             2 (0010)

BUG=b:175896481
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot

Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com>
Change-Id: I2ace17e8fff12d3f5de15a35f609265d8b6ed6b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48948
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/volteer/variants/copano/Makefile.inc

@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+romstage-y += memory.c

src/mainboard/google/volteer/variants/copano/memory.c

@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+
+static const struct lpddr4x_cfg copano_memcfg = {
+	/* DQ byte map */
+	.dq_map = {
+		[0] = {
+			{ 7,  3,  1,  4,  0,  5,  2,  6, }, /* DDR0_DQ0[7:0] */
+			{ 13, 14, 8,  10, 9,  15, 11, 12 }, /* DDR0_DQ1[7:0] */
+		},
+		[1] = {
+			{ 1,  2,  7,  6,  3,  5,  4,  0, }, /* DDR1_DQ0[7:0] */
+			{ 14, 15, 13, 10,  8, 11, 12, 9  }, /* DDR1_DQ1[7:0] */
+		},
+		[2] = {
+			{ 11, 15, 10, 9,  8, 12, 13, 14, }, /* DDR2_DQ0[7:0] */
+			{ 5,  6,  4,  0,  7,  2,  3,  1  }, /* DDR2_DQ1[7:0] */
+		},
+		[3] = {
+			{ 11, 15, 10, 9, 13, 12, 14,  8, }, /* DDR3_DQ0[7:0] */
+			{ 0,  5,  6,  4,  1,  2,  7,  3  }, /* DDR3_DQ1[7:0] */
+		},
+		[4] = {
+			{ 7,  2,  3,  1,  4,  0,  5,  6, }, /* DDR4_DQ0[7:0] */
+			{ 13, 14,  8, 12, 10,  9, 15, 11 }, /* DDR4_DQ1[7:0] */
+		},
+		[5] = {
+			{ 7,  3,  2,  1,  6,  4,  0,  5, }, /* DDR5_DQ0[7:0] */
+			{ 15, 14, 12, 8, 11, 13,  9,  10 }, /* DDR5_DQ1[7:0] */
+		},
+		[6] = {
+			{ 11, 10, 15, 12, 8,  9, 14, 13, }, /* DDR6_DQ0[7:0] */
+			{ 6,  0,  5,  4,  3,  2,  7,  1  }, /* DDR6_DQ1[7:0] */
+		},
+		[7] = {
+			{ 9, 10, 11,  8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */
+			{ 0,  5,  4,  7,  1,  6,  3,  2  }, /* DDR7_DQ1[7:0] */
+		},
+	},
+
+	/* DQS CPU<>DRAM map */
+	.dqs_map = {
+		[0] = { 0, 1 },  /* DDR0_DQS[1:0] */
+		[1] = { 0, 1 },  /* DDR1_DQS[1:0] */
+		[2] = { 1, 0 },  /* DDR2_DQS[1:0] */
+		[3] = { 1, 0 },  /* DDR3_DQS[1:0] */
+		[4] = { 0, 1 },  /* DDR4_DQS[1:0] */
+		[5] = { 0, 1 },  /* DDR5_DQS[1:0] */
+		[6] = { 1, 0 },  /* DDR6_DQS[1:0] */
+		[7] = { 1, 0 },  /* DDR7_DQS[1:0] */
+	},
+
+	.ect = 1, /* Enable Early Command Training */
+};
+
+static const struct ddr_memory_cfg board_memcfg = {
+	.mem_type = MEMTYPE_LPDDR4X,
+	.lpddr4_cfg = &copano_memcfg
+};
+
+const struct ddr_memory_cfg *variant_memory_params(void)
+{
+	return &board_memcfg;
+}

src/mainboard/google/volteer/variants/copano/memory/Makefile.inc

@@ -2,6 +2,6 @@
 ## This is an auto-generated file. Do not edit!!
 
 SPD_SOURCES =
-SPD_SOURCES += lp4x-spd-1.hex      # ID = 0(0b0000)  Parts = MT53E512M64D4NW-046 WT:E, H9HCNNNCRMBLPR-NEE, MT53D512M64D4NW-046 WT:F
+SPD_SOURCES += lp4x-spd-1.hex      # ID = 0(0b0000)  Parts = MT53D512M64D4NW-046 WT:F, H9HCNNNCRMBLPR-NEE
 SPD_SOURCES += lp4x-spd-4.hex      # ID = 1(0b0001)  Parts = MT53D1G64D4NW-046 WT:A
 SPD_SOURCES += lp4x-spd-3.hex      # ID = 2(0b0010)  Parts = H9HCNNNFBMBLPR-NEE

src/mainboard/google/volteer/variants/copano/memory/dram_id.generated.txt

@@ -1,6 +1,5 @@
 DRAM Part Name                 ID to assign
-MT53E512M64D4NW-046 WT:E       0 (0000)
+MT53D512M64D4NW-046 WT:F       0 (0000)
 H9HCNNNCRMBLPR-NEE             0 (0000)
 MT53D1G64D4NW-046 WT:A         1 (0001)
 H9HCNNNFBMBLPR-NEE             2 (0010)
-MT53D512M64D4NW-046 WT:F       0 (0000)

src/mainboard/google/volteer/variants/copano/memory/mem_list_variant.txt

@@ -1,5 +1,4 @@
-MT53E512M64D4NW-046 WT:E
+MT53D512M64D4NW-046 WT:F
 H9HCNNNCRMBLPR-NEE
 MT53D1G64D4NW-046 WT:A
 H9HCNNNFBMBLPR-NEE
-MT53D512M64D4NW-046 WT:F