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mb/ibm/sbp1: Drop SuperIO code 

The SuperIO is not used so don't enable decoding of 0xE2 and
drop all code using it. It's not even required for the virtual
UART on 0x3f8 to work.

Add the virtual UART on 0x3f8 as ACPI device.

TEST: Verified on SBP1 that serial still works.

Change-Id: I8e431a0c8417435cc6e3ba16f97ff080e1656a7b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Patrick Rudolph 2023-07-20 08:56:54 +02:00 committed by Felix Held
parent ef4f2cd38e
commit 6e0de5d9cc
4 changed files with 15 additions and 15 deletions
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1
src/mainboard/ibm/sbp1/Kconfig
View File

@ -8,7 +8,6 @@ config BOARD_SPECIFIC_OPTIONS
select MEMORY_MAPPED_TPM select MEMORY_MAPPED_TPM
select MAINBOARD_USES_FSP2_0 select MAINBOARD_USES_FSP2_0
select SOC_INTEL_SAPPHIRERAPIDS_SP select SOC_INTEL_SAPPHIRERAPIDS_SP
select SUPERIO_ASPEED_AST2400 # Check if AST2400 is compatible
select HAVE_ACPI_TABLES select HAVE_ACPI_TABLES
select MAINBOARD_USES_IFD_GBE_REGION select MAINBOARD_USES_IFD_GBE_REGION

13
src/mainboard/ibm/sbp1/acpi/platform.asl
View File

@ -21,6 +21,19 @@ Field (DBG0, ByteAcc, Lock, Preserve)
IO81, 8 IO81, 8
} }
/* Virtual UART on 0x3f8 */
Scope(\_SB) {
Device(COM1) {
Name(_HID, EisaId("PNP0501"))
Name(_UID, 0x01)
Name(_STA,0x0F)
Name(_CRS, ResourceTemplate() {
IO(Decode16, 0x03F8, 0x03F8, 0x00, 0x08)
IRQNoFlags() { 4 }
})
}
}
/* /*
* The _PTS method (Prepare To Sleep) is called before the OS is * The _PTS method (Prepare To Sleep) is called before the OS is
* entering a sleep state. The sleep state number is passed in Arg0 * entering a sleep state. The sleep state number is passed in Arg0

7
src/mainboard/ibm/sbp1/bootblock.c
View File

@ -8,24 +8,21 @@
#include <soc/intel/common/block/lpc/lpc_def.h> #include <soc/intel/common/block/lpc/lpc_def.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
#include <soc/pcr_ids.h> #include <soc/pcr_ids.h>
#include <superio/aspeed/ast2400/ast2400.h>
#include <superio/aspeed/common/aspeed.h>
#define ASPEED_SIO_PORT 0x2E
#define PCR_DMI_LPCIOD 0x2770 #define PCR_DMI_LPCIOD 0x2770
#define PCR_DMI_LPCIOE 0x2774 #define PCR_DMI_LPCIOE 0x2774
void bootblock_mainboard_early_init(void) void bootblock_mainboard_early_init(void)
{ {
uint16_t lpciod = LPC_IOD_COMA_RANGE; uint16_t lpciod = LPC_IOD_COMA_RANGE;
uint16_t lpcioe = (LPC_IOE_SUPERIO_2E_2F | LPC_IOE_COMA_EN); uint16_t lpcioe = LPC_IOE_COMA_EN;
/* Open IO windows: 0x3f8 for com1 */ /* Open IO windows: 0x3f8 for com1 */
pcr_or32(PID_DMI, PCR_DMI_LPCIOD, lpciod); pcr_or32(PID_DMI, PCR_DMI_LPCIOD, lpciod);
/* LPC I/O enable: com1 */ /* LPC I/O enable: com1 */
pcr_or32(PID_DMI, PCR_DMI_LPCIOE, lpcioe); pcr_or32(PID_DMI, PCR_DMI_LPCIOE, lpcioe);
/* Enable com1 (0x3f8) and superio (0x2e) */ /* Enable com1 (0x3f8) */
pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, lpciod); pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, lpciod);
pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, lpcioe); pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, lpcioe);
} }

9
src/mainboard/ibm/sbp1/devicetree.cb
View File

@ -6,15 +6,6 @@ chip soc/intel/xeon_sp/spr
device pci 16.3 off end # Serial controller: Intel Corporation Device 1be3 device pci 16.3 off end # Serial controller: Intel Corporation Device 1be3
device pci 1f.0 on # Intel device 1b81: PCH eSPI controller device pci 1f.0 on # Intel device 1b81: PCH eSPI controller
chip superio/common
device pnp 2e.0 on
chip superio/aspeed/ast2400
register "use_espi" = "1"
device pnp 2e.2 off end # SUART1
device pnp 2e.3 off end # SUART2
end
end
end
chip drivers/ipmi # BMC KCS chip drivers/ipmi # BMC KCS
device pnp ca2.0 on end device pnp ca2.0 on end
register "bmc_i2c_address" = "0x20" register "bmc_i2c_address" = "0x20"