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Remove some warnings. 

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4686 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Myles Watson 2009-09-29 14:56:15 +00:00
parent 5e54871375
commit 6e2357676f
16 changed files with 42 additions and 40 deletions
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2
src/arch/i386/include/arch/smp/mpspec.h
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@ -239,7 +239,7 @@ void smp_write_processor(struct mp_config_table *mc,
unsigned int featureflag);
void smp_write_processors(struct mp_config_table *mc);
void smp_write_bus(struct mp_config_table *mc,
unsigned char id, char *bustype);
unsigned char id, const char *bustype);
void smp_write_ioapic(struct mp_config_table *mc,
unsigned char id, unsigned char ver,
unsigned long apicaddr);

2
src/arch/i386/smp/mpspec.c
View File

@ -134,7 +134,7 @@ void smp_write_processors(struct mp_config_table *mc)
}
void smp_write_bus(struct mp_config_table *mc,
unsigned char id, char *bustype)
unsigned char id, const char *bustype)
{
struct mpc_config_bus *mpc;
mpc = smp_next_mpc_entry(mc);

2
src/cpu/amd/car/copy_and_run.c
View File

@ -4,7 +4,7 @@
*/
#if CONFIG_CBFS == 1
void cbfs_and_run_core(char*, unsigned ebp);
void cbfs_and_run_core(const char*, unsigned ebp);
static void copy_and_run(void)
{

2
src/cpu/amd/car/post_cache_as_ram.c
View File

@ -27,10 +27,10 @@ static void inline __attribute__((always_inline)) memcopy(void *dest, const voi
static void vErrata343(void)
{
#ifdef BU_CFG2_MSR
msr_t msr;
unsigned int uiMask = 0xFFFFFFF7;
#ifdef BU_CFG2_MSR
msr = rdmsr(BU_CFG2_MSR);
msr.hi &= uiMask; // set bit 35 to 0
wrmsr(BU_CFG2_MSR, msr);

3
src/cpu/amd/model_fxx/init_cpus.c
View File

@ -347,7 +347,8 @@ static unsigned init_cpus(unsigned cpu_init_detectedx)
lapic_write(LAPIC_MSG_REG, (apicid<<24) | 0x44); // bsp can not check it before stop_this_cpu
set_init_ram_access();
#if CONFIG_MEM_TRAIN_SEQ == 1
train_ram_on_node(id.nodeid, id.coreid, sysinfo, STOP_CAR_AND_CPU);
train_ram_on_node(id.nodeid, id.coreid, sysinfo,
(unsigned) STOP_CAR_AND_CPU);
#endif
STOP_CAR_AND_CPU();

6
src/cpu/amd/model_fxx/processor_name.c
View File

@ -143,7 +143,7 @@ static inline unsigned int cpuid_ecx(unsigned int op)
return ecx;
}
static inline void strcpy(char *dst, char *src)
static inline void strcpy(char *dst, const char *src)
{
while (*src) *dst++ = *src++;
}
@ -151,7 +151,9 @@ static inline void strcpy(char *dst, char *src)
int init_processor_name(void)
{
#if CONFIG_K8_REV_F_SUPPORT == 0
u32 EightBitBrandId;
#endif
u32 BrandId;
u32 BrandTableIndex;
u32 NN;
@ -159,7 +161,7 @@ int init_processor_name(void)
msr_t progmsr;
int i;
char *processor_name_string=NULL;
const char *processor_name_string=NULL;
char program_string[48];
unsigned int *program_values = (unsigned int *)program_string;

4
src/cpu/x86/lapic/lapic_cpu_init.c
View File

@ -37,10 +37,11 @@ char *lowmem_backup_ptr;
int lowmem_backup_size;
#endif
extern char _secondary_start[];
static void copy_secondary_start_to_1m_below(void)
{
#if CONFIG_RAMBASE >= 0x100000
extern char _secondary_start[];
extern char _secondary_start_end[];
unsigned long code_size;
unsigned long start_eip;
@ -74,7 +75,6 @@ static int lapic_start_cpu(unsigned long apicid)
int timeout;
unsigned long send_status, accept_status, start_eip;
int j, num_starts, maxlvt;
extern char _secondary_start[];
/*
* Starting actual IPI sequence...

7
src/devices/hypertransport.c
View File

@ -392,9 +392,9 @@ unsigned int hypertransport_scan_chain(struct bus *bus,
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
//let't record the device of last ht device, So we can set the Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE
unsigned real_last_unitid;
uint8_t real_last_pos;
device_t real_last_dev;
unsigned real_last_unitid=0;
uint8_t real_last_pos=0;
device_t real_last_dev=NULL;
unsigned end_used = 0;
#endif
@ -553,7 +553,6 @@ unsigned int hypertransport_scan_chain(struct bus *bus,
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
if(offset_unitid && (ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) {
uint16_t flags;
int i;
device_t last_func = 0;
flags = pci_read_config16(real_last_dev, real_last_pos + PCI_CAP_FLAGS);
flags &= ~0x1f;

2
src/include/device/device.h
View File

@ -15,7 +15,7 @@ struct smbus_bus_operations;
/* Chip operations */
struct chip_operations {
void (*enable_dev)(struct device *dev);
char *name;
const char *name;
};
#define CHIP_NAME(X) .name = X,

7
src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c
View File

@ -253,11 +253,13 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
};
struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
struct sys_info *sysinfo = (void*)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
int needs_reset; int i;
int needs_reset;
unsigned bsp_apicid = 0;
#if K8_SET_FIDVID == 1
struct cpuid_result cpuid1;
#endif
if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
@ -361,6 +363,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_smbus();
#if 0
int i;
for(i=0;i<4;i++) {
activate_spd_rom(&cpu[i]);
dump_smbus_registers();

2
src/mainboard/amd/serengeti_cheetah/irq_tables.c
View File

@ -58,7 +58,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
addr &= ~15;
/* This table must be betweeen 0xf0000 & 0x100000 */
printk_info("Writing IRQ routing tables to 0x%x...", addr);
printk_info("Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr);
v = (uint8_t *)(addr);

2
src/northbridge/amd/amdk8/coherent_ht.c
View File

@ -1661,10 +1661,10 @@ static int apply_cpu_errata_fixes(unsigned nodes)
unsigned node;
int needs_reset = 0;
for(node = 0; node < nodes; node++) {
#if CONFIG_K8_REV_F_SUPPORT == 0
device_t dev;
uint32_t cmd;
dev = NODE_MC(node);
#if CONFIG_K8_REV_F_SUPPORT == 0
if (is_cpu_pre_c0()) {
/* Errata 66

6
src/northbridge/amd/amdk8/exit_from_self.c
View File

@ -25,7 +25,7 @@ void exit_from_self(int controllers, const struct mem_controller *ctrl,
u32 pcidev;
u8 bitmask;
u8 is_post_rev_g;
u32 cpuid;
u32 local_cpuid;
for (i = 0; i < controllers; i++) {
if (!sysinfo->ctrl_present[i])
@ -36,8 +36,8 @@ void exit_from_self(int controllers, const struct mem_controller *ctrl,
continue;
}
cpuid = pci_read_config32(ctrl[i].f3, 0xfc);
is_post_rev_g = ((cpuid & 0xfff00) > 0x50f00);
local_cpuid = pci_read_config32(ctrl[i].f3, 0xfc);
is_post_rev_g = ((local_cpuid & 0xfff00) > 0x50f00);
/* ChipKill */
dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);

25
src/northbridge/amd/amdk8/raminit_f.c
View File

@ -1859,7 +1859,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
int latencies;
int latency;
int index;
int value;
int val;
u32 spd_device = ctrl->channel0[i];
if (!(meminfo->dimm_mask & (1 << i))) {
@ -1893,14 +1893,14 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
}
/* Read the min_cycle_time for this latency */
value = spd_read_byte(spd_device, latency_indicies[index]);
if (value < 0) goto hw_error;
val = spd_read_byte(spd_device, latency_indicies[index]);
if (val < 0) goto hw_error;
value = convert_to_linear(value);
val = convert_to_linear(val);
/* All is good if the selected clock speed
* is what I need or slower.
*/
if (value <= min_cycle_time) {
if (val <= min_cycle_time) {
continue;
}
/* Otherwise I have an error, disable the dimm */
@ -2508,7 +2508,9 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *
{
uint32_t dword;
uint32_t dwordx;
#if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */
unsigned SlowAccessMode = 0;
#endif
long dimm_mask = meminfo->dimm_mask & 0x0f;
@ -3007,8 +3009,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
tsc_t tsc, tsc0[8];
printk_debug("sdram_enable: tsc0[8]: %p", &tsc0[0]);
#endif
uint32_t dword;
#endif
/* Error if I don't have memory */
if (memory_end_k(ctrl, controllers) == 0) {
@ -3017,7 +3019,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
/* Before enabling memory start the memory clocks */
for (i = 0; i < controllers; i++) {
uint32_t dtl, dch;
uint32_t dch;
if (!sysinfo->ctrl_present[ i ])
continue;
dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
@ -3083,20 +3085,13 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
}
#endif
#if 0
/* Set the DqsRcvEnTrain bit */
dword = pci_read_config32(ctrl[i].f2, DRAM_CTRL);
dword |= DC_DqsRcvEnTrain;
pci_write_config32(ctrl[i].f2, DRAM_CTRL, dword);
#endif
pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
dcl |= DCL_InitDram;
pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
}
for (i = 0; i < controllers; i++) {
uint32_t dcl, dch, dcm;
uint32_t dcl, dcm;
if (!sysinfo->ctrl_present[ i ])
continue;
/* Skip everything if I don't have any memory on this controller */

6
src/northbridge/amd/amdk8/raminit_f_dqs.c
View File

@ -522,7 +522,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st
unsigned PatternA;
unsigned PatternB;
unsigned TestAddr0, TestAddr0B, TestAddr1, TestAddr1B = 0;
unsigned TestAddr0, TestAddr0B, TestAddr1 = 0, TestAddr1B = 0;
unsigned CurrRcvrCHADelay = 0;
@ -530,7 +530,9 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st
unsigned is_Width128 = sysinfo->meminfo[ctrl->node_id].is_Width128;
#if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
unsigned cpu_f0_f1;
#endif
if(Pass == DQS_FIRST_PASS) {
InitDQSPos4RcvrEn(ctrl);
@ -2094,7 +2096,7 @@ static void copy_and_run_ap_code_in_car(unsigned ret_addr);
static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall)
{
if(coreid) return; // only do it on core0
struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
struct sys_info *sysinfox = (void*)((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
wait_till_sysinfo_in_ram(); // use pci to get it
if(sysinfox->mem_trained[nodeid] == 0x80) {

4
src/southbridge/amd/amd8111/amd8111_lpc.c
View File

@ -76,7 +76,7 @@ static void setup_ioapic(void)
l = (unsigned long *) ioapic_base;
ioapicregvalues[0].value_high = bsp_apicid<<(56-32);
printk_debug("amd8111: ioapic bsp_apicid = %02x\n", bsp_apicid);
printk_debug("amd8111: ioapic bsp_apicid = %02lx\n", bsp_apicid);
for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
i++, a++) {
@ -101,7 +101,7 @@ static void enable_hpet(struct device *dev)
pci_write_config32(dev,0xa0, 0xfed00001);
hpet_address = pci_read_config32(dev,0xa0)& 0xfffffffe;
printk_debug("enabling HPET @0x%x\n", hpet_address);
printk_debug("enabling HPET @0x%lx\n", hpet_address);
}