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soc/amd/picasso: move smm_region to soc/amd/common/block/cpu/noncar

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The same functionality is needed on Cezanne.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I40f9d2fe7d144e94369a417225bcca0a299d1f45
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Felix Held 2021-02-08 18:16:07 +01:00
parent fa265fdc3b
commit 6e2f5f2ee7
2 changed files with 54 additions and 51 deletions
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56
src/soc/amd/common/block/cpu/noncar/memmap.c
View file

@ -1,9 +1,14 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <stdint.h> #include <amdblocks/memmap.h>
#include <console/console.h> #include <console/console.h>
#include <cbmem.h> #include <cbmem.h>
#include <amdblocks/memmap.h> #include <cpu/amd/msr.h>
#include <cpu/x86/smm.h>
#include <fsp/util.h>
#include <FspGuids.h>
#include <memrange.h>
#include <stdint.h>
void memmap_stash_early_dram_usage(void) void memmap_stash_early_dram_usage(void)
{ {
@ -27,3 +32,50 @@ const struct memmap_early_dram *memmap_get_early_dram_usage(void)
return e; return e;
} }
/*
* For data stored in TSEG, ensure TValid is clear so R/W access can reach
* the DRAM when not in SMM.
*/
static void clear_tvalid(void)
{
msr_t hwcr = rdmsr(HWCR_MSR);
msr_t mask = rdmsr(SMM_MASK_MSR);
int tvalid = !!(mask.lo & SMM_TSEG_VALID);
if (hwcr.lo & SMM_LOCK) {
if (!tvalid) /* not valid but locked means still accessible */
return;
printk(BIOS_ERR, "Error: can't clear TValid, already locked\n");
return;
}
mask.lo &= ~SMM_TSEG_VALID;
wrmsr(SMM_MASK_MSR, mask);
}
void smm_region(uintptr_t *start, size_t *size)
{
static int once;
struct range_entry tseg;
int status;
*start = 0;
*size = 0;
status = fsp_find_range_hob(&tseg, AMD_FSP_TSEG_HOB_GUID.b);
if (status < 0) {
printk(BIOS_ERR, "Error: unable to find TSEG HOB\n");
return;
}
*start = (uintptr_t)range_entry_base(&tseg);
*size = range_entry_size(&tseg);
if (!once) {
clear_tvalid();
once = 1;
}
}

49
src/soc/amd/picasso/memmap.c
View file

@ -3,60 +3,11 @@
#include <assert.h> #include <assert.h>
#include <stdint.h> #include <stdint.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/smm.h>
#include <cpu/amd/msr.h>
#include <arch/bert_storage.h> #include <arch/bert_storage.h>
#include <memrange.h> #include <memrange.h>
#include <fsp/util.h> #include <fsp/util.h>
#include <FspGuids.h> #include <FspGuids.h>
/*
* For data stored in TSEG, ensure TValid is clear so R/W access can reach
* the DRAM when not in SMM.
*/
static void clear_tvalid(void)
{
msr_t hwcr = rdmsr(HWCR_MSR);
msr_t mask = rdmsr(SMM_MASK_MSR);
int tvalid = !!(mask.lo & SMM_TSEG_VALID);
if (hwcr.lo & SMM_LOCK) {
if (!tvalid) /* not valid but locked means still accessible */
return;
printk(BIOS_ERR, "Error: can't clear TValid, already locked\n");
return;
}
mask.lo &= ~SMM_TSEG_VALID;
wrmsr(SMM_MASK_MSR, mask);
}
void smm_region(uintptr_t *start, size_t *size)
{
static int once;
struct range_entry tseg;
int status;
*start = 0;
*size = 0;
status = fsp_find_range_hob(&tseg, AMD_FSP_TSEG_HOB_GUID.b);
if (status < 0) {
printk(BIOS_ERR, "Error: unable to find TSEG HOB\n");
return;
}
*start = (uintptr_t)range_entry_base(&tseg);
*size = range_entry_size(&tseg);
if (!once) {
clear_tvalid();
once = 1;
}
}
void bert_reserved_region(void **start, size_t *size) void bert_reserved_region(void **start, size_t *size)
{ {
struct range_entry bert; struct range_entry bert;