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soc/intel/tigerlake: Fix PMC config

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Fix PMC base address for tigerlake.

BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: Id13222eb5498a5704c11d6b4d1e83212bd8b2723
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This commit is contained in:
Ravi Sarawadi 2019-12-17 00:05:44 -08:00 committed by Subrata Banik
parent 0c89c297e6
commit 6e33797841
1 changed files with 1 additions and 1 deletions
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2
src/soc/intel/tigerlake/bootblock/pch.c
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@ -40,7 +40,7 @@
#include <soc/pcr_ids.h> #include <soc/pcr_ids.h>
#include <soc/pm.h> #include <soc/pm.h>
#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_TGP 0x0600 #define PCR_PSF3_TO_SHDW_PMC_REG_BASE_TGP 0x1100
#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP 0x0980 #define PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP 0x0980
#define PCR_PSFX_TO_SHDW_BAR0 0 #define PCR_PSFX_TO_SHDW_BAR0 0
#define PCR_PSFX_TO_SHDW_BAR1 0x4 #define PCR_PSFX_TO_SHDW_BAR1 0x4