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soc/amd/sabrina: Add XHCI configuration 

Add xhci 2 controller support for additional USB port/ Dummy setting

BUG=b:214413631
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I5c8885bf46ddbfc85b31585a4da7f746c1a6bcd5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Jon Murphy 2022-02-24 14:37:04 -07:00 committed by Felix Held
parent 96bb0ba9e7
commit 6e368f79ec
4 changed files with 34 additions and 12 deletions
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1
src/include/device/pci_ids.h
View File

@ -599,6 +599,7 @@
#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_XHCI 0x1639
#define PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_XHCI0 0x1503
#define PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_XHCI1 0x1504
#define PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_XHCI2 0x1505
#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF0 0x15E8
#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF1 0x15E9
#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF2 0x15EA

2
src/soc/amd/sabrina/chipset.cb
View File

@ -64,7 +64,7 @@ chip soc/amd/sabrina
end
device pci 08.2 alias gpp_bridge_b off end # Internal GPP Bridge 1 to Bus B
device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C
device pci 0.0 alias dummy_function_c off end # PCIe Dummy Function
device pci 0.0 alias xhci_2 off end # Might also be a dummy device with different PCI DID
end
device pci 14.0 alias smbus on end # primary FCH function

4
src/soc/amd/sabrina/include/soc/pci_devs.h
View File

@ -87,6 +87,10 @@
#define PCIE_GPP_C_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC)
#define SOC_PCIE_GPP_C_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC)
#define XHCI2_DEV 0x0
#define XHCI2_FUNC 0
#define XHCI2_DEVFN PCI_DEVFN(XHCI2_DEV, XHCI2_FUNC)
/* SMBUS */
#define SMBUS_DEV 0x14
#define SMBUS_FUNC 0

39
src/soc/amd/sabrina/xhci.c
View File

@ -6,6 +6,7 @@
#include <amdblocks/smi.h>
#include <bootstate.h>
#include <device/device.h>
#include <device/pci_ids.h>
#include <drivers/usb/pci_xhci/pci_xhci.h>
#include <soc/pci_devs.h>
#include <soc/smi.h>
@ -22,6 +23,12 @@ static const struct sci_source xhci_sci_sources[] = {
.gpe = GEVENT_31,
.direction = SMI_SCI_LVL_HIGH,
.level = SMI_SCI_EDG
},
{
.scimap = SMITYPE_XHC2_PME,
.gpe = GEVENT_31,
.direction = SMI_SCI_LVL_HIGH,
.level = SMI_SCI_EDG
}
};
@ -30,25 +37,35 @@ enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe)
if (dev->bus->dev->path.type != DEVICE_PATH_PCI)
return CB_ERR_ARG;
if (dev->bus->dev->path.pci.devfn != PCIE_ABC_A_DEVFN)
return CB_ERR_ARG;
if (dev->path.type != DEVICE_PATH_PCI)
return CB_ERR_ARG;
if (dev->path.pci.devfn == XHCI0_DEVFN)
*gpe = xhci_sci_sources[0].gpe;
else if (dev->path.pci.devfn == XHCI1_DEVFN)
*gpe = xhci_sci_sources[1].gpe;
else
return CB_ERR_ARG;
if (dev->bus->dev->path.pci.devfn == PCIE_ABC_A_DEVFN) {
if (dev->path.pci.devfn == XHCI0_DEVFN) {
*gpe = xhci_sci_sources[0].gpe;
return CB_SUCCESS;
} else if (dev->path.pci.devfn == XHCI1_DEVFN) {
*gpe = xhci_sci_sources[1].gpe;
return CB_SUCCESS;
}
} else if (dev->bus->dev->path.pci.devfn == PCIE_GPP_C_DEVFN) {
if (dev->path.pci.devfn == XHCI2_DEVFN
&& dev->device == PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_XHCI2) {
*gpe = xhci_sci_sources[2].gpe;
return CB_SUCCESS;
}
}
return CB_SUCCESS;
return CB_ERR_ARG;
}
static void configure_xhci_sci(void *unused)
{
gpe_configure_sci(xhci_sci_sources, ARRAY_SIZE(xhci_sci_sources));
const struct device *xhci_2 = DEV_PTR(xhci_2);
if (xhci_2->device == PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_XHCI2)
gpe_configure_sci(xhci_sci_sources, ARRAY_SIZE(xhci_sci_sources));
else
gpe_configure_sci(xhci_sci_sources, ARRAY_SIZE(xhci_sci_sources) - 1);
}
BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, configure_xhci_sci, NULL);