doc/mb/ocp: update Delta Lake documentation
Update Delta Lake documentation following ww30 to ww33 build/test/release cycle. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I9bb3a4daa423503d487045f2f069a43d2cc09129 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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# OCP Delta Lake
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This page describes coreboot support status for the [OCP] (Open Compute Project)
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Delta Lake server platform.
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Delta Lake server platform. This page is updated following each 4-weeks
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build/test/release cycle.
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## Introduction
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- FSP blob: The blob (Intel Cooper Lake Scalable Processor Firmware Support Package)
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is not yet available to the public. It will be made public some time after the MP
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(Mass Production) of CooperLake Scalable Processor when the FSP is mature.
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- Microcode: Not yet available to the public.
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- Microcode: Available through github.com:otcshare/Intel-Generic-Microcode.git.
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- ME binary: Not yet available to the public.
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## Payload
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- Type 2 -- Baseboard Information
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- Type 3 -- System Enclosure or Chassis
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- Type 4 -- Processor Information
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- Type 7 -- Cache Information
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- Type 8 -- Port Connector Information
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- Type 9 -- PCI Slot Information
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- Type 11 -- OEM String
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- Type 13 -- BIOS Language Information
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- Type 16 -- Physical Memory Array
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- Type 19 -- Memory Array Mapped Address
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- Type 32 -- System Boot Information
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- Type 38 -- IPMI Device Information
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- Type 127 -- End-of-Table
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- BMC integration:
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- BMC readiness check
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- IPMI commands
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- watchdog timer
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- POST complete pin acknowledgement
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- Check BMC version: ipmidump -device
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- SEL record generation
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- Early serial output
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- port 80h direct to GPIO
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- ACPI tables: APIC/DSDT/FACP/FACS/HPET/MCFG/SPMI/SRAT/SLIT/SSDT
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- ACPI tables: APIC/DMAR/DSDT/FACP/FACS/HPET/MCFG/SPMI/SRAT/SLIT/SSDT
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- Skipping memory training upon subsequent reboots by using MRC cache
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- BMC crash dump
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- Error injection through ITP
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- Versions
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- Check FSP version: cbmem | grep LB_TAG_PLATFORM_BLOB_VERSION
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- Check Microcode version: cat /proc/cpuinfo | grep microcode
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- Devices:
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- Boot drive
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- NIC card
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- All 5 data drives
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- Power button
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- localboot
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- netboot from IPv6
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## Stress/performance tests passed
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- OS warm reboot overnight (6 hours)
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- Mprime test (6 hours)
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- MLC (Intel Memory Latency Check)
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- Linkpack
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## Firmware configurations
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[ChromeOS VPD] is used to store most of the firmware configurations.
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VPD variables supported are:
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- firmware_version: This variable holds overall firmware version. coreboot
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uses that value to populate smbios type 1 version field.
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- DeltaLake specific VPDs: check mb/ocp/deltalake/vpd.h.
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## Known issues
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- Even though CPX-SP FSP is based on FSP 2.2 framework, it does not
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support FSP_USES_CB_STACK. An IPS ticket is filed with Intel.
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- VT-d is not supported. An IPS ticket is filed with Intel.
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- PCIe bifuration is not supported. An IPS ticket is filed with Intel.
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- ME based power capping. This is a bug in ME. An IPS ticket is filed
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with Intel.
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- RO_VPD region as well as other RO regions are not write protected.
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- HECI is not set up correctly, so BMC is not able to get PCH and DIMM
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temperature sensor readings.
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temperature sensor readings. An IPS ticket is filed.
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## Feature gaps
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- Delta Lake DVT is not supported, as we only have Delta Lake EVT servers
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at the moment.
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- SMBIOS:
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- Type 7 -- Cache Information
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- Type 16 -- Physical Memory Array
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- Type 17 -- Memory Device
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- Type 38 -- IPMI Device Information
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- Type 19 -- Memory Array Mapped Address
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- Type 41 -- Onboard Devices Extended Information
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- ACPI:
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- DMAR
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- Hardware error injection, detection, reporting
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- PFR/CBnT
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- RO_VPD region as well as other RO regions are not write protected.
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## Technology
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+------------------------+---------------------------------------------+
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| BMC | Aspeed AST 2500 |
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+------------------------+---------------------------------------------+
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| PCH | Intel Lewisburg C621 |
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| PCH | Intel Lewisburg C620 Series |
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+------------------------+---------------------------------------------+
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```
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