binaryPI: Enable EARLY_CBMEM_INIT

Also moves postcar stack to CBMEM.

Change-Id: I0263af9561e0367bbbde4d5c3190039f4c3047a0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19347
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

src/cpu/amd/pi/romstage.c

@@ -14,10 +14,12 @@
  */
 
 #include <arch/cpu.h>
+#include <cbmem.h>
 #include <cpu/amd/car.h>
 #include <cpu/x86/mtrr.h>
 #include <console/console.h>
 #include <program_loading.h>
+#include <romstage_handoff.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
 #include <northbridge/amd/agesa/state_machine.h>
 
@@ -28,12 +30,20 @@ void asmlinkage early_all_cores(void)
 
 void * asmlinkage romstage_main(unsigned long bist)
 {
-	uintptr_t stack_top = CACHE_TMP_RAMTOP;
+	int s3resume = 0;
 	u8 initial_apic_id = cpuid_ebx(1) >> 24;
 
 	/* Only BSP returns from here. */
 	cache_as_ram_main(bist, initial_apic_id);
 
+	cbmem_recovery(s3resume);
+
+	romstage_handoff_init(s3resume);
+
+	uintptr_t stack_top = romstage_ram_stack_base(HIGH_ROMSTAGE_STACK_SIZE,
+		ROMSTAGE_STACK_CBMEM);
+	stack_top += HIGH_ROMSTAGE_STACK_SIZE;
+
 	printk(BIOS_DEBUG, "Move CAR stack.\n");
 	return (void*)stack_top;
 }

src/northbridge/amd/pi/Kconfig

@@ -17,7 +17,7 @@ config NORTHBRIDGE_AMD_PI
 	bool
 	default y if CPU_AMD_PI
 	default n
-	select LATE_CBMEM_INIT
+	select CBMEM_TOP_BACKUP
 
 if NORTHBRIDGE_AMD_PI