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soc/amd/cezanne/acpi: Use IO addresses for ACPI block 

This causes the linux kernel to complain:
32/64X address mismatch in FADT/Pm1aEventBlock: 0x00000400/0x00000000FED80800
32/64X address mismatch in FADT/Pm1aControlBlock: 0x00000404/0x00000000FED80804
32/64X address mismatch in FADT/PmTimerBlock: 0x00000408/0x00000000FED80808
32/64X address mismatch in FADT/Gpe0Block: 0x00000420/0x00000000FED80814

The linux kernel also verifies that the PM Timer block only uses IO
ports.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I612b6bfb67d8559127ab2ee8a2fb828493820e31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Raul E Rangel 2021-02-19 16:01:05 -07:00 committed by Felix Held
parent 8e425b0245
commit 6e3f383927
1 changed files with 9 additions and 13 deletions
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22
src/soc/amd/cezanne/acpi.c
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@ -85,35 +85,31 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
ACPI_FADT_REMOTE_POWER_ON; ACPI_FADT_REMOTE_POWER_ON;
fadt->flags |= cfg->fadt_flags; /* additional board-specific flags */ fadt->flags |= cfg->fadt_flags; /* additional board-specific flags */
/* fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
* The Cezanne PPR defines the ACPI registers starting at PMx00000500. This translates
* to 0x300 + 0x500 = 0x800 which is identical to acpimmio_acpi.
*/
fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_MEMORY;
fadt->x_pm1a_evt_blk.bit_width = 32; fadt->x_pm1a_evt_blk.bit_width = 32;
fadt->x_pm1a_evt_blk.bit_offset = 0; fadt->x_pm1a_evt_blk.bit_offset = 0;
fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
fadt->x_pm1a_evt_blk.addrl = (u32)acpimmio_acpi + MMIO_ACPI_PM1_EVT_BLK; fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
fadt->x_pm1a_evt_blk.addrh = 0x0; fadt->x_pm1a_evt_blk.addrh = 0x0;
fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_MEMORY; fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm1a_cnt_blk.bit_width = 16; fadt->x_pm1a_cnt_blk.bit_width = 16;
fadt->x_pm1a_cnt_blk.bit_offset = 0; fadt->x_pm1a_cnt_blk.bit_offset = 0;
fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
fadt->x_pm1a_cnt_blk.addrl = (u32)acpimmio_acpi + MMIO_ACPI_PM1_CNT_BLK; fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
fadt->x_pm1a_cnt_blk.addrh = 0x0; fadt->x_pm1a_cnt_blk.addrh = 0x0;
fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_MEMORY; fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_width = 32;
fadt->x_pm_tmr_blk.bit_offset = 0; fadt->x_pm_tmr_blk.bit_offset = 0;
fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
fadt->x_pm_tmr_blk.addrl = (u32)acpimmio_acpi + MMIO_ACPI_PM_TMR_BLK; fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
fadt->x_pm_tmr_blk.addrh = 0x0; fadt->x_pm_tmr_blk.addrh = 0x0;
fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_MEMORY; fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_gpe0_blk.bit_width = 64; fadt->x_gpe0_blk.bit_width = 64;
fadt->x_gpe0_blk.bit_offset = 0; fadt->x_gpe0_blk.bit_offset = 0;
fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
fadt->x_gpe0_blk.addrl = (u32)acpimmio_acpi + MMIO_ACPI_GPE0_BLK; fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
fadt->x_gpe0_blk.addrh = 0x0; fadt->x_gpe0_blk.addrh = 0x0;
} }