diff --git a/src/soc/intel/cannonlake/elog.c b/src/soc/intel/cannonlake/elog.c
index 5319cff897..2ec6b410df 100644
--- a/src/soc/intel/cannonlake/elog.c
+++ b/src/soc/intel/cannonlake/elog.c
@@ -76,11 +76,11 @@ static void pch_log_power_and_resets(struct chipset_power_state *ps)
 		elog_add_event(ELOG_TYPE_THERM_TRIP);
 
 	/* PWR_FLR Power Failure */
-	if (ps->gen_pmcon_b & PWR_FLR)
+	if (ps->gen_pmcon_a & PWR_FLR)
 		elog_add_event(ELOG_TYPE_POWER_FAIL);
 
 	/* SUS Well Power Failure */
-	if (ps->gen_pmcon_b & SUS_PWR_FLR)
+	if (ps->gen_pmcon_a & SUS_PWR_FLR)
 		elog_add_event(ELOG_TYPE_SUS_POWER_FAIL);
 
 	/* TCO Timeout */
@@ -97,7 +97,7 @@ static void pch_log_power_and_resets(struct chipset_power_state *ps)
 		elog_add_event(ELOG_TYPE_RTC_RESET);
 
 	/* Host Reset Status */
-	if (ps->gen_pmcon_b & HOST_RST_STS)
+	if (ps->gen_pmcon_a & HOST_RST_STS)
 		elog_add_event(ELOG_TYPE_SYSTEM_RESET);
 
 	/* ACPI Wake Event */
diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c
index 16c4db6c5d..8c166cf389 100644
--- a/src/soc/intel/cannonlake/pmutil.c
+++ b/src/soc/intel/cannonlake/pmutil.c
@@ -217,7 +217,7 @@ int soc_prev_sleep_state(const struct chipset_power_state *ps,
 	* S5 because the PCH does not set the WAK_STS bit when waking
 	* from a true G3 state.
 	*/
-	if (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR))
+	if (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR))
 		prev_sleep_state = ACPI_S5;
 
 	/*
@@ -233,7 +233,7 @@ int soc_prev_sleep_state(const struct chipset_power_state *ps,
 		if (!deep_s3_enabled())
 			mask |= SUS_PWR_FLR;
 
-		if (ps->gen_pmcon_b & mask)
+		if (ps->gen_pmcon_a & mask)
 			prev_sleep_state = ACPI_S5;
 	}