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soc/intel/{adl,common}: Add ASPM setting in pcie_rp_config 

This change provides config for devicetree to control ASPM per port

BUG=b:220079865
TEST=Build FW and run stress exceed 2500 cycles on taeko.

Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I19b5f3dc8d95e153301d777492c921ce582ba988
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62919
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kevin Chang 2022-03-18 21:04:07 +08:00 committed by Tim Wawrzynczak
parent 4b1f25d82f
commit 6e52c1da4a
2 changed files with 34 additions and 0 deletions
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22
src/soc/intel/alderlake/fsp_params.c
View File

@ -297,6 +297,26 @@ static int get_l1_substate_control(enum L1_substates_control ctl)
return ctl - 1; return ctl - 1;
} }
/*
* Chip config parameter pcie_rp_aspm uses (UPD value + 1) because
* a UPD value of 0 for pcie_rp_aspm means disabled. In order to ensure
* that the mainboard setting does not disable ASPM incorrectly, chip
* config parameter values are offset by 1 with 0 meaning use FSP UPD default.
* get_aspm_control() ensures that the right UPD value is set in fsp_params.
* 0: Use FSP UPD default
* 1: Disable ASPM
* 2: L0s only
* 3: L1 only
* 4: L0s and L1
* 5: Auto configuration
*/
static unsigned int get_aspm_control(enum ASPM_control ctl)
{
if ((ctl > ASPM_AUTO) || (ctl == ASPM_DEFAULT))
ctl = ASPM_AUTO;
return ctl - 1;
}
/* This function returns the VccIn Aux Imon IccMax values for ADL-P SKU's */ /* This function returns the VccIn Aux Imon IccMax values for ADL-P SKU's */
static uint16_t get_vccin_aux_imon_iccmax(void) static uint16_t get_vccin_aux_imon_iccmax(void)
{ {
@ -632,6 +652,8 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg,
s_cfg->PcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER); s_cfg->PcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER);
s_cfg->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG); s_cfg->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG);
s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT); s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT);
if (rp_cfg->pcie_rp_aspm)
s_cfg->PcieRpAspm[i] = get_aspm_control(rp_cfg->pcie_rp_aspm);
} }
} }

12
src/soc/intel/common/block/include/intelblocks/pcie_rp.h
View File

@ -42,6 +42,16 @@ enum L1_substates_control {
L1_SS_L1_2, L1_SS_L1_2,
}; };
/* This enum is for passing into an FSP UPD, typically ASPM */
enum ASPM_control {
ASPM_DEFAULT,
ASPM_DISABLE,
ASPM_L0S,
ASPM_L1,
ASPM_L0S_L1,
ASPM_AUTO,
};
/* PCIe Root Ports */ /* PCIe Root Ports */
struct pcie_rp_config { struct pcie_rp_config {
/* CLKOUT_PCIE_P/N# used by this root port as per schematics. */ /* CLKOUT_PCIE_P/N# used by this root port as per schematics. */
@ -51,6 +61,8 @@ struct pcie_rp_config {
enum pcie_rp_flags flags; enum pcie_rp_flags flags;
/* PCIe RP L1 substate */ /* PCIe RP L1 substate */
enum L1_substates_control PcieRpL1Substates; enum L1_substates_control PcieRpL1Substates;
/* PCIe RP ASPM */
enum ASPM_control pcie_rp_aspm;
}; };
/* /*