GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

sb/amd/sb700: Add option to increase SPI speed to 33MHz 

Some SB700-based systems and ROMs support high speed (33MHz) SPI
access instead of the power-on default 16.5MHz.  Add an option
to enable high speed SPI access in the bootblock, and set the
default value to Disabled.  This greatly decreases boot time on
SB700-based systems, especiall when a large payload is in use.

On a KGPE-D16 with a Petitboot (Linux + initramfs) payload, the
command prompt was accessible within 20 seconds of power on, which
incidentally is faster than the proprietary BIOS on the same machine
could even reach the GRUB bootloader.

Change-Id: Iadbd9bb611754262ef75a5e5a6ee4390a46e45cf
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Test: Booted KGPE-D16 with Linux payload
Reviewed-on: https://review.coreboot.org/16306
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Timothy Pearson 2016-08-23 15:41:05 -05:00
parent 3b0e761dd5
commit 6e5421d2a8
2 changed files with 44 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/southbridge/amd/sb700/Kconfig
View File

@ -25,6 +25,16 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy
select HAVE_HARD_RESET select HAVE_HARD_RESET
select SMBUS_HAS_AUX_CHANNELS select SMBUS_HAS_AUX_CHANNELS
config SOUTHBRIDGE_AMD_SB700_33MHZ_SPI
bool "Enable high speed SPI clock"
default n
help
When set, the SPI clock will run at 33MHz instead
of the compatibility mode 16.5MHz. Note that not
all ROMs are capable of 33MHz operation, so you
will need to verify this option is appropriate for
the ROM you are using.
# Set for southbridge SP5100 which also uses SB700 driver # Set for southbridge SP5100 which also uses SB700 driver
config SOUTHBRIDGE_AMD_SUBTYPE_SP5100 config SOUTHBRIDGE_AMD_SUBTYPE_SP5100
bool bool

34
src/southbridge/amd/sb700/bootblock.c
View File

@ -20,6 +20,10 @@
#define IO_MEM_PORT_DECODE_ENABLE_5 0x48 #define IO_MEM_PORT_DECODE_ENABLE_5 0x48
#define IO_MEM_PORT_DECODE_ENABLE_6 0x4a #define IO_MEM_PORT_DECODE_ENABLE_6 0x4a
#define SPI_BASE_ADDRESS 0xa0
#define SPI_CONTROL_1 0xc
#define TEMPORARY_SPI_BASE_ADDRESS 0xfec10000
/* /*
* Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
@ -92,7 +96,37 @@ static void sb700_enable_rom(void)
pci_io_write_config8(dev, IO_MEM_PORT_DECODE_ENABLE_6, reg8); pci_io_write_config8(dev, IO_MEM_PORT_DECODE_ENABLE_6, reg8);
} }
static void sb700_configure_rom(void)
{
pci_devfn_t dev;
uint32_t dword;
dev = PCI_DEV(0, 0x14, 3);
if (IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700_33MHZ_SPI)) {
uint32_t prev_spi_cfg;
volatile uint32_t *spi_mmio;
/* Temporarily set up SPI access to change SPI speed */
prev_spi_cfg = dword = pci_io_read_config32(dev, SPI_BASE_ADDRESS);
dword &= ~(0x7ffffff << 5); /* SPI_BaseAddr */
dword |= TEMPORARY_SPI_BASE_ADDRESS & (0x7ffffff << 5);
dword |= (0x1 << 1); /* SpiRomEnable = 1 */
pci_io_write_config32(dev, SPI_BASE_ADDRESS, dword);
spi_mmio = (void *)(TEMPORARY_SPI_BASE_ADDRESS + SPI_CONTROL_1);
dword = *spi_mmio;
dword &= ~(0x3 << 12); /* NormSpeed = 0x1 */
dword |= (0x1 << 12);
*spi_mmio = dword;
/* Restore previous SPI access */
pci_io_write_config32(dev, SPI_BASE_ADDRESS, prev_spi_cfg);
}
}
static void bootblock_southbridge_init(void) static void bootblock_southbridge_init(void)
{ {
sb700_enable_rom(); sb700_enable_rom();
sb700_configure_rom();
} }