GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

This patch adds support for mainboard iBASE:MB899 

based on Kontron 986LCD-M
changed superIO chip to w83627ehg, dropping MIDI
dropped second superIO at 4e
changed superIO-addr from 2e to 4e
adjusted irq_tables.c and devicetree.cb
dropped setup of 3xGBit-Ethernet
adjusted IRQ-map (using values from mainboard/intel/d945gclf)
disabled parts about HD-audio (missing on that board)

Signed-off-by: Bernhard M. Wiedemann <corebootbmw@lsmod.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5599 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Bernhard M. Wiedemann 2010-05-30 12:56:17 +00:00 committed by Stefan Reinauer
parent 1c60c88679
commit 6e554de098
24 changed files with 2474 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/mainboard/Kconfig
View File

@ -48,6 +48,8 @@ config VENDOR_GIGABYTE
bool "GIGABYTE"
config VENDOR_HP
bool "HP"
config VENDOR_IBASE
bool "iBase"
config VENDOR_IBM
bool "IBM"
config VENDOR_IEI
@ -219,6 +221,11 @@ config MAINBOARD_VENDOR
default "HP"
depends on VENDOR_HP
config MAINBOARD_VENDOR
string
default "iBase"
depends on VENDOR_IBASE
config MAINBOARD_VENDOR
string
default "IBM"
@ -421,6 +428,7 @@ source "src/mainboard/emulation/Kconfig"
source "src/mainboard/getac/Kconfig"
source "src/mainboard/gigabyte/Kconfig"
source "src/mainboard/hp/Kconfig"
source "src/mainboard/ibase/Kconfig"
source "src/mainboard/ibm/Kconfig"
source "src/mainboard/iei/Kconfig"
source "src/mainboard/intel/Kconfig"

8
src/mainboard/ibase/Kconfig Normal file
View File

@ -0,0 +1,8 @@
choice
prompt "Mainboard model"
depends on VENDOR_IBASE
source "src/mainboard/ibase/mb899/Kconfig"
endchoice

73
src/mainboard/ibase/mb899/Kconfig Normal file
View File

@ -0,0 +1,73 @@
config BOARD_IBASE_MB899
bool "MB899"
select ARCH_X86
select CPU_INTEL_CORE
select CPU_INTEL_SOCKET_MFCPGA478
select NORTHBRIDGE_INTEL_I945
select SOUTHBRIDGE_INTEL_I82801GX
select SUPERIO_WINBOND_W83627EHG
select BOARD_HAS_FADT
select GENERATE_ACPI_TABLES
select GENERATE_PIRQ_TABLE
select GENERATE_MP_TABLE
select HAVE_HARD_RESET
select HAVE_ACPI_RESUME
select HAVE_MAINBOARD_RESOURCES
select MMCONF_SUPPORT
select USE_PRINTK_IN_CAR
select HAVE_SMI_HANDLER
select BOARD_ROMSIZE_KB_512
select USE_DCACHE_RAM
select GFXUMA
select TINY_BOOTBLOCK
config MAINBOARD_DIR
string
default ibase/mb899
depends on BOARD_IBASE_MB899
config DCACHE_RAM_BASE
hex
default 0xffdf8000
depends on BOARD_IBASE_MB899
config DCACHE_RAM_SIZE
hex
default 0x8000
depends on BOARD_IBASE_MB899
config MAINBOARD_PART_NUMBER
string
default "MB899"
depends on BOARD_IBASE_MB899
config MMCONF_BASE_ADDRESS
hex
default 0xf0000000
depends on BOARD_IBASE_MB899
config IRQ_SLOT_COUNT
int
default 18
depends on BOARD_IBASE_MB899
config MAX_CPUS
int
default 4
depends on BOARD_IBASE_MB899
config MAX_PHYSICAL_CPUS
int
default 2
depends on BOARD_IBASE_MB899
config FALLBACK_VGA_BIOS_FILE
string
default "amipci_01.20"
depends on BOARD_IBASE_MB899
config HAVE_ACPI_SLIC
bool
default n
depends on BOARD_IBASE_MB899

22
src/mainboard/ibase/mb899/Makefile.inc Normal file
View File

@ -0,0 +1,22 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2008 coresystems GmbH
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
obj-y += rtl8168.o
smmobj-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.o

49
src/mainboard/ibase/mb899/acpi/ec.asl Normal file
View File

@ -0,0 +1,49 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
Device(EC0)
{
Name (_HID, EISAID("PNP0C09"))
Name (_UID, 1)
Method (_CRS, 0)
{
Name (ECMD, ResourceTemplate()
{
IO (Decode16, 0x62, 0x62, 0, 1)
IO (Decode16, 0x66, 0x66, 0, 1)
})
Return (ECMD)
}
Method (_REG, 2)
{
// This method is needed by Windows XP/2000
// for EC initialization before a driver
// is loaded
}
Name (_GPE, 23) // GPI07 / GPE23 -> Runtime SCI
// TODO EC Query methods
// TODO Scope _SB devices for AC power, LID, Power button
}

86
src/mainboard/ibase/mb899/acpi/i945_pci_irqs.asl Normal file
View File

@ -0,0 +1,86 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* This is board specific information: IRQ routing for the
* i945
*/
// PCI Interrupt Routing
Method(_PRT)
{
If (PICM) {
Return (Package() {
// PCIe Graphics 0:1.0
Package() { 0x0001ffff, 0, 0, 16 },
Package() { 0x0001ffff, 1, 0, 17 },
Package() { 0x0001ffff, 2, 0, 18 },
Package() { 0x0001ffff, 3, 0, 19 },
// Onboard graphics (IGD) 0:2.0
Package() { 0x0002ffff, 0, 0, 16 },
// High Definition Audio 0:1b.0
//Package() { 0x001bffff, 0, 0, 16 },
// PCIe Root Ports 0:1c.x
Package() { 0x001cffff, 0, 0, 16 },
Package() { 0x001cffff, 1, 0, 17 },
Package() { 0x001cffff, 2, 0, 18 },
Package() { 0x001cffff, 3, 0, 19 },
// USB and EHCI 0:1d.x
Package() { 0x001dffff, 0, 0, 23 },
Package() { 0x001dffff, 1, 0, 19 },
Package() { 0x001dffff, 2, 0, 18 },
Package() { 0x001dffff, 3, 0, 16 },
// AC97/IDE 0:1e.2, 0:1e.3
Package() { 0x001effff, 0, 0, 17 },
Package() { 0x001effff, 1, 0, 20 },
// LPC device 0:1f.0
Package() { 0x001fffff, 0, 0, 18 },
Package() { 0x001fffff, 1, 0, 19},
})
} Else {
Return (Package() {
// PCIe Graphics 0:1.0
Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
// Onboard graphics (IGD) 0:2.0
Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
// High Definition Audio 0:1b.0
//Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
// PCIe Root Ports 0:1c.x
Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
// USB and EHCI 0:1d.x
Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
// AC97/IDE 0:1e.2, 0:1e.3
Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
// LPC device 0:1f.0
Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
})
}
}

103
src/mainboard/ibase/mb899/acpi/ich7_pci_irqs.asl Normal file
View File

@ -0,0 +1,103 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* This is board specific information: IRQ routing for the
* 0:1e.0 PCI bridge of the ICH7
*/
If (PICM) {
Return (Package() {
Package() { 0x0000ffff, 0, 0, 16},
Package() { 0x0001ffff, 0, 0, 20},
Package() { 0x0001ffff, 1, 0, 21},
Package() { 0x0001ffff, 2, 0, 22},
Package() { 0x0001ffff, 3, 0, 23},
Package() { 0x0002ffff, 0, 0, 21},
Package() { 0x0002ffff, 1, 0, 22},
Package() { 0x0002ffff, 2, 0, 23},
Package() { 0x0002ffff, 3, 0, 20},
Package() { 0x0003ffff, 0, 0, 22},
Package() { 0x0003ffff, 1, 0, 23},
Package() { 0x0003ffff, 2, 0, 20},
Package() { 0x0003ffff, 3, 0, 21},
Package() { 0x0004ffff, 0, 0, 23},
Package() { 0x0004ffff, 1, 0, 20},
Package() { 0x0004ffff, 2, 0, 21},
Package() { 0x0004ffff, 3, 0, 22},
Package() { 0x0005ffff, 0, 0, 19},
Package() { 0x0005ffff, 1, 0, 18},
Package() { 0x0005ffff, 2, 0, 17},
Package() { 0x0005ffff, 3, 0, 16},
Package() { 0x0006ffff, 0, 0, 18},
Package() { 0x0006ffff, 1, 0, 17},
Package() { 0x0006ffff, 2, 0, 16},
Package() { 0x0006ffff, 3, 0, 19},
Package() { 0x0009ffff, 0, 0, 21},
Package() { 0x0009ffff, 1, 0, 22},
Package() { 0x0009ffff, 2, 0, 23},
Package() { 0x0009ffff, 3, 0, 20},
})
} Else {
Return (Package() {
Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0},
Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKE, 0},
Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0},
Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKG, 0},
Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0},
Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKF, 0},
Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKG, 0},
Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKH, 0},
Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKE, 0},
Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKG, 0},
Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKH, 0},
Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKE, 0},
Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKF, 0},
Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKH, 0},
Package() { 0x0004ffff, 1, \_SB.PCI0.LPCB.LNKE, 0},
Package() { 0x0004ffff, 2, \_SB.PCI0.LPCB.LNKF, 0},
Package() { 0x0004ffff, 3, \_SB.PCI0.LPCB.LNKG, 0},
Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKD, 0},
Package() { 0x0005ffff, 1, \_SB.PCI0.LPCB.LNKC, 0},
Package() { 0x0005ffff, 2, \_SB.PCI0.LPCB.LNKB, 0},
Package() { 0x0005ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},
Package() { 0x0006ffff, 0, \_SB.PCI0.LPCB.LNKC, 0},
Package() { 0x0006ffff, 1, \_SB.PCI0.LPCB.LNKB, 0},
Package() { 0x0006ffff, 2, \_SB.PCI0.LPCB.LNKA, 0},
Package() { 0x0006ffff, 3, \_SB.PCI0.LPCB.LNKD, 0},
Package() { 0x0009ffff, 0, \_SB.PCI0.LPCB.LNKF, 0},
Package() { 0x0009ffff, 1, \_SB.PCI0.LPCB.LNKG, 0},
Package() { 0x0009ffff, 2, \_SB.PCI0.LPCB.LNKH, 0},
Package() { 0x0009ffff, 3, \_SB.PCI0.LPCB.LNKE, 0},
})
}

91
src/mainboard/ibase/mb899/acpi/platform.asl Normal file
View File

@ -0,0 +1,91 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* The APM port can be used for generating software SMIs */
OperationRegion (APMP, SystemIO, 0xb2, 2)
Field (APMP, ByteAcc, NoLock, Preserve)
{
APMC, 8, // APM command
APMS, 8 // APM status
}
/* Port 80 POST */
OperationRegion (POST, SystemIO, 0x80, 1)
Field (POST, ByteAcc, Lock, Preserve)
{
DBG0, 8
}
/* SMI I/O Trap */
Method(TRAP, 1, Serialized)
{
Store (Arg0, SMIF) // SMI Function
Store (0, TRP0) // Generate trap
Return (SMIF) // Return value of SMI handler
}
/* The _PIC method is called by the OS to choose between interrupt
* routing via the i8259 interrupt controller or the APIC.
*
* _PIC is called with a parameter of 0 for i8259 configuration and
* with a parameter of 1 for Local Apic/IOAPIC configuration.
*/
Method(_PIC, 1)
{
// Remember the OS' IRQ routing choice.
Store(Arg0, PICM)
}
/* The _PTS method (Prepare To Sleep) is called before the OS is
* entering a sleep state. The sleep state number is passed in Arg0
*/
Method(_PTS,1)
{
// Call a trap so SMI can prepare for Sleep as well.
// TRAP(0x55)
}
/* The _WAK method is called on system wakeup */
Method(_WAK,1)
{
// CPU specific part
// Notify PCI Express slots in case a card
// was inserted while a sleep state was active.
// Are we going to S3?
If (LEqual(Arg0, 3)) {
// ..
}
// Are we going to S4?
If (LEqual(Arg0, 4)) {
// ..
}
// TODO: Windows XP SP2 P-State restore
Return(Package(){0,0})
}

92
src/mainboard/ibase/mb899/acpi/superio.asl Normal file
View File

@ -0,0 +1,92 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
Device (SIO1)
{
Name (_HID, EISAID("PNP0A05"))
Name (_UID, 1)
Device (UAR1)
{
Name(_HID, EISAID("PNP0501"))
Name(_UID, 1)
Name(_DDN, "COM1")
Method (_STA, 0)
{
// always enable for now
Return (0x0f)
}
Method (_DIS, 0) { /* NOOP */ }
Name (_PRS, ResourceTemplate() {
StartDependentFn(0, 1) {
IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8)
IRQNoFlags() { 4 }
} EndDependentFn()
})
Method (_CRS, 0)
{
Return(ResourceTemplate() {
IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8)
IRQNoFlags() { 4 }
})
}
// Some methods need an implementation here:
// missing: _STA, _DIS, _CRS, _PRS,
// missing: _SRS, _PS0, _PS3
}
Device (UAR2)
{
Name(_HID, EISAID("PNP0501"))
Name(_UID, 2)
Name(_DDN, "COM2")
Method (_STA, 0)
{
// always enable for now
Return (0x0f)
}
Method (_DIS, 0) { /* NOOP */ }
Name (_PRS, ResourceTemplate() {
StartDependentFn(0, 1) {
IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8)
IRQNoFlags() { 3 }
} EndDependentFn()
})
Method (_CRS, 0)
{
Return(ResourceTemplate() {
IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8)
IRQNoFlags() { 3 }
})
}
// Some methods need an implementation here:
// missing: _STA, _DIS, _CRS, _PRS,
// missing: _SRS, _PS0, _PS3
}
}

94
src/mainboard/ibase/mb899/acpi/thermal.asl Normal file
View File

@ -0,0 +1,94 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
// Thermal Zone
Scope (\_TZ)
{
ThermalZone (THRM)
{
// FIXME these could/should be read from the
// GNVS area, so they can be controlled by
// coreboot
Name(TC1V, 0x04)
Name(TC2V, 0x03)
Name(TSPV, 0x64)
// At which temperature should the OS start
// active cooling?
Method (_AC0, 0, Serialized)
{
Return (0xf5c) // Value for Rocky
}
// Method (_AC1, 0, Serialized)
// {
// Return (0xf5c)
// }
// Critical shutdown temperature
Method (_CRT, 0, Serialized)
{
Return (Add (0x0aac, 0x50)) // FIXME
}
// CPU throttling start temperature
Method (_PSV, 0, Serialized)
{
Return (0xaaf) // FIXME
}
// Get DTS Temperature
Method (_TMP, 0, Serialized)
{
Return (0xaac) // FIXME
}
// Processors used for active cooling
Method (_PSL, 0, Serialized)
{
If (MPEN) {
Return (Package() {\_PR.CPU1, \_PR.CPU2})
}
Return (Package() {\_PR.CPU1})
}
// TC1 value for passive cooling
Method (_TC1, 0, Serialized)
{
Return (TC1V)
}
// TC2 value for passive cooling
Method (_TC2, 0, Serialized)
{
Return (TC2V)
}
// Sampling period for passive cooling
Method (_TSP, 0, Serialized)
{
Return (TSPV)
}
}
}

43
src/mainboard/ibase/mb899/acpi/video.asl Normal file
View File

@ -0,0 +1,43 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
// Brightness write
Method (BRTW, 1, Serialized)
{
// TODO
}
// Hot Key Display Switch
Method (HKDS, 1, Serialized)
{
// TODO
}
// Lid Switch Display Switch
Method (LSDS, 1, Serialized)
{
// TODO
}
// Brightness Notification
Method(BRTN,1,Serialized)
{
// TODO (no displays defined yet)
}

273
src/mainboard/ibase/mb899/acpi_tables.c Normal file
View File

@ -0,0 +1,273 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <types.h>
#include <string.h>
#include <console/console.h>
#include <arch/acpi.h>
#include <arch/acpigen.h>
#include <arch/smp/mpspec.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/x86/msr.h>
#include "dmi.h"
extern const unsigned char AmlCode[];
#if CONFIG_HAVE_ACPI_SLIC
unsigned long acpi_create_slic(unsigned long current);
#endif
#include "../../../southbridge/intel/i82801gx/i82801gx_nvs.h"
static void acpi_create_gnvs(global_nvs_t *gnvs)
{
memset((void *)gnvs, 0, sizeof(*gnvs));
gnvs->apic = 1;
gnvs->mpen = 1; /* Enable Multi Processing */
/* Enable both COM ports */
gnvs->cmap = 0x01;
gnvs->cmbp = 0x01;
/* IGD Displays */
gnvs->ndid = 3;
gnvs->did[0] = 0x80000100;
gnvs->did[1] = 0x80000240;
gnvs->did[2] = 0x80000410;
gnvs->did[3] = 0x80000410;
gnvs->did[4] = 0x00000005;
}
static void acpi_create_intel_hpet(acpi_hpet_t * hpet)
{
#define HPET_ADDR 0xfed00000ULL
acpi_header_t *header = &(hpet->header);
acpi_addr_t *addr = &(hpet->addr);
memset((void *) hpet, 0, sizeof(acpi_hpet_t));
/* fill out header fields */
memcpy(header->signature, "HPET", 4);
memcpy(header->oem_id, OEM_ID, 6);
memcpy(header->oem_table_id, "COREBOOT", 8);
memcpy(header->asl_compiler_id, ASLC, 4);
header->length = sizeof(acpi_hpet_t);
header->revision = 1;
/* fill out HPET address */
addr->space_id = 0; /* Memory */
addr->bit_width = 64;
addr->bit_offset = 0;
addr->addrl = HPET_ADDR & 0xffffffff;
addr->addrh = HPET_ADDR >> 32;
hpet->id = 0x8086a201; /* Intel */
hpet->number = 0x00;
hpet->min_tick = 0x0080;
header->checksum =
acpi_checksum((void *) hpet, sizeof(acpi_hpet_t));
}
#define IO_APIC_ADDR 0xfec00000UL
unsigned long acpi_fill_madt(unsigned long current)
{
/* Local APICs */
current = acpi_create_madt_lapics(current);
/* IOAPIC */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
2, IO_APIC_ADDR, 0);
/* INT_SRC_OVR */
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 0, 2, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
return current;
}
unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
{
generate_cpu_entries();
return (unsigned long) (acpigen_get_current());
}
unsigned long acpi_fill_slit(unsigned long current)
{
// Not implemented
return current;
}
unsigned long acpi_fill_srat(unsigned long current)
{
/* No NUMA, no SRAT */
return current;
}
void smm_setup_structures(void *gnvs, void *tcg, void *smi1);
#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10)
unsigned long write_acpi_tables(unsigned long start)
{
unsigned long current;
int i;
acpi_rsdp_t *rsdp;
acpi_rsdt_t *rsdt;
acpi_xsdt_t *xsdt;
acpi_hpet_t *hpet;
acpi_madt_t *madt;
acpi_mcfg_t *mcfg;
acpi_fadt_t *fadt;
acpi_facs_t *facs;
#if CONFIG_HAVE_ACPI_SLIC
acpi_header_t *slic;
#endif
acpi_header_t *ssdt;
acpi_header_t *dsdt;
current = start;
/* Align ACPI tables to 16byte */
ALIGN_CURRENT;
printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
/* We need at least an RSDP and an RSDT Table */
rsdp = (acpi_rsdp_t *) current;
current += sizeof(acpi_rsdp_t);
ALIGN_CURRENT;
rsdt = (acpi_rsdt_t *) current;
current += sizeof(acpi_rsdt_t);
ALIGN_CURRENT;
xsdt = (acpi_xsdt_t *) current;
current += sizeof(acpi_xsdt_t);
ALIGN_CURRENT;
/* clear all table memory */
memset((void *) start, 0, current - start);
acpi_write_rsdp(rsdp, rsdt, xsdt);
acpi_write_rsdt(rsdt);
acpi_write_xsdt(xsdt);
/*
* We explicitly add these tables later on:
*/
printk(BIOS_DEBUG, "ACPI: * HPET\n");
hpet = (acpi_hpet_t *) current;
current += sizeof(acpi_hpet_t);
ALIGN_CURRENT;
acpi_create_intel_hpet(hpet);
acpi_add_table(rsdp, hpet);
/* If we want to use HPET Timers Linux wants an MADT */
printk(BIOS_DEBUG, "ACPI: * MADT\n");
madt = (acpi_madt_t *) current;
acpi_create_madt(madt);
current += madt->header.length;
ALIGN_CURRENT;
acpi_add_table(rsdp, madt);
printk(BIOS_DEBUG, "ACPI: * MCFG\n");
mcfg = (acpi_mcfg_t *) current;
acpi_create_mcfg(mcfg);
current += mcfg->header.length;
ALIGN_CURRENT;
acpi_add_table(rsdp, mcfg);
printk(BIOS_DEBUG, "ACPI: * FACS\n");
facs = (acpi_facs_t *) current;
current += sizeof(acpi_facs_t);
ALIGN_CURRENT;
acpi_create_facs(facs);
dsdt = (acpi_header_t *) current;
memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
current += dsdt->length;
memcpy(dsdt, &AmlCode, dsdt->length);
ALIGN_CURRENT;
/* Pack GNVS into the ACPI table area */
for (i=0; i < dsdt->length; i++) {
if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
printk(BIOS_DEBUG, "ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
*(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
break;
}
}
/* And fill it */
acpi_create_gnvs((global_nvs_t *)current);
current += 0x100;
ALIGN_CURRENT;
/* And tell SMI about it */
smm_setup_structures((void *)current, NULL, NULL);
/* We patched up the DSDT, so we need to recalculate the checksum */
dsdt->checksum = 0;
dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt,
dsdt->length);
#if CONFIG_HAVE_ACPI_SLIC
printk(BIOS_DEBUG, "ACPI: * SLIC\n");
slic = (acpi_header_t *)current;
current += acpi_create_slic(current);
ALIGN_CURRENT;
acpi_add_table(rsdp, slic);
#endif
printk(BIOS_DEBUG, "ACPI: * FADT\n");
fadt = (acpi_fadt_t *) current;
current += sizeof(acpi_fadt_t);
ALIGN_CURRENT;
acpi_create_fadt(fadt, facs, dsdt);
acpi_add_table(rsdp, fadt);
printk(BIOS_DEBUG, "ACPI: * SSDT\n");
ssdt = (acpi_header_t *)current;
acpi_create_ssdt_generator(ssdt, "COREBOOT");
current += ssdt->length;
acpi_add_table(rsdp, ssdt);
ALIGN_CURRENT;
printk(BIOS_DEBUG, "current = %lx\n", current);
printk(BIOS_DEBUG, "ACPI: * DMI (Linux workaround)\n");
memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE);
#if CONFIG_WRITE_HIGH_TABLES == 1
memcpy((void *)current, dmi_table, DMI_TABLE_SIZE);
current += DMI_TABLE_SIZE;
ALIGN_CURRENT;
#endif
printk(BIOS_INFO, "ACPI: done.\n");
return current;
}

23
src/mainboard/ibase/mb899/chip.h Normal file
View File

@ -0,0 +1,23 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2008 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
extern struct chip_operations mainboard_ops;
struct mainboard_config {
int nothing;
};

194
src/mainboard/ibase/mb899/cmos.layout Normal file
View File

@ -0,0 +1,194 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2008 coresystems GmbH
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
# -----------------------------------------------------------------
entries
#start-bit length config config-ID name
#0 8 r 0 seconds
#8 8 r 0 alarm_seconds
#16 8 r 0 minutes
#24 8 r 0 alarm_minutes
#32 8 r 0 hours
#40 8 r 0 alarm_hours
#48 8 r 0 day_of_week
#56 8 r 0 day_of_month
#64 8 r 0 month
#72 8 r 0 year
# -----------------------------------------------------------------
# Status Register A
#80 4 r 0 rate_select
#84 3 r 0 REF_Clock
#87 1 r 0 UIP
# -----------------------------------------------------------------
# Status Register B
#88 1 r 0 auto_switch_DST
#89 1 r 0 24_hour_mode
#90 1 r 0 binary_values_enable
#91 1 r 0 square-wave_out_enable
#92 1 r 0 update_finished_enable
#93 1 r 0 alarm_interrupt_enable
#94 1 r 0 periodic_interrupt_enable
#95 1 r 0 disable_clock_updates
# -----------------------------------------------------------------
# Status Register C
#96 4 r 0 status_c_rsvd
#100 1 r 0 uf_flag
#101 1 r 0 af_flag
#102 1 r 0 pf_flag
#103 1 r 0 irqf_flag
# -----------------------------------------------------------------
# Status Register D
#104 7 r 0 status_d_rsvd
#111 1 r 0 valid_cmos_ram
# -----------------------------------------------------------------
# Diagnostic Status Register
#112 8 r 0 diag_rsvd1
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
#120 264 r 0 unused
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
385 1 e 4 last_boot
388 4 r 0 reboot_bits
#390 2 r 0 unused?
# -----------------------------------------------------------------
# coreboot config options: console
392 3 e 5 baud_rate
395 4 e 6 debug_level
#399 1 r 0 unused
# coreboot config options: cpu
400 1 e 2 hyper_threading
#401 7 r 0 unused
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
#411 5 r 0 unused
# coreboot config options: bootloader
416 512 s 0 boot_devices
#928 40 r 0 unused
# coreboot config options: mainboard specific options
948 2 e 8 cpufan_cruise_control
950 2 e 8 sysfan_cruise_control
952 4 e 9 cpufan_speed
#956 4 e 10 cpufan_temperature
960 4 e 9 sysfan_speed
#964 4 e 10 sysfan_temperature
968 1 e 2 ethernet1
969 1 e 2 ethernet2
970 1 e 2 ethernet3
#971 13 r 0 unused
# coreboot config options: check sums
984 16 h 0 check_sum
#1000 24 r 0 amd_reserved
# ram initialization internal data
1024 8 r 0 C0WL0REOST
1032 8 r 0 C1WL0REOST
1040 8 r 0 RCVENMT
1048 4 r 0 C0DRT1
1052 4 r 0 C1DRT1
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
5 0 115200
5 1 57600
5 2 38400
5 3 19200
5 4 9600
5 5 4800
5 6 2400
5 7 1200
6 1 Emergency
6 2 Alert
6 3 Critical
6 4 Error
6 5 Warning
6 6 Notice
6 7 Info
6 8 Debug
6 9 Spew
7 0 Disable
7 1 Enable
7 2 Keep
# Fan Cruise Control
8 0 Disabled
8 1 Speed
#8 2 Thermal
# Fan Speed (Rotations per Minute)
9 0 5625
9 1 5192
9 2 4753
9 3 4326
9 4 3924
9 5 3552
9 6 3214
9 7 2909
9 8 2636
9 9 2393
9 10 2177
9 11 1985
9 12 1814
9 13 1662
9 14 1527
9 15 1406
#
# Temperature (°C/°F)
#10 0 30/86
#10 1 33/91
#10 2 36/96
#10 3 39/102
#10 4 42/107
#10 5 45/113
#10 6 48/118
#10 7 51/123
#10 8 54/129
#10 9 57/134
#10 10 60/140
#10 11 63/145
#10 12 66/150
#10 13 69/156
#10 14 72/161
#10 15 75/167
# -----------------------------------------------------------------
checksums
checksum 392 983 984

101
src/mainboard/ibase/mb899/devicetree.cb Normal file
View File

@ -0,0 +1,101 @@
chip northbridge/intel/i945
device lapic_cluster 0 on
chip cpu/intel/socket_mFCPGA478
device lapic 0 on end
end
end
device pci_domain 0 on
device pci 00.0 on end # host bridge
device pci 01.0 off end # i945 PCIe root port
device pci 02.0 on end # vga controller
device pci 02.1 on end # display controller
chip southbridge/intel/i82801gx
register "pirqa_routing" = "0x05"
register "pirqb_routing" = "0x07"
register "pirqc_routing" = "0x05"
register "pirqd_routing" = "0x07"
register "pirqe_routing" = "0x80"
register "pirqf_routing" = "0x80"
register "pirqg_routing" = "0x80"
register "pirqh_routing" = "0x06"
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
# 2 SCI (if corresponding GPIO_EN bit is also set)
register "gpi13_routing" = "1"
register "ide_legacy_combined" = "0x0"
register "ide_enable_primary" = "0x1"
register "ide_enable_secondary" = "0x0"
register "sata_ahci" = "0x1"
#device pci 1b.0 on end # High Definition Audio
device pci 1c.0 on end # PCIe
device pci 1c.1 on end # PCIe
device pci 1c.2 on end # PCIe
#device pci 1c.3 off end # PCIe port 4
#device pci 1c.4 off end # PCIe port 5
#device pci 1c.5 off end # PCIe port 6
device pci 1d.0 on end # USB UHCI
device pci 1d.1 on end # USB UHCI
device pci 1d.2 on end # USB UHCI
device pci 1d.3 on end # USB UHCI
device pci 1d.7 on end # USB2 EHCI
device pci 1e.0 on end # PCI bridge
#device pci 1e.2 off end # AC'97 Audio
#device pci 1e.3 off end # AC'97 Modem
device pci 1f.0 on # LPC bridge
chip superio/winbond/w83627ehg
device pnp 4e.0 off # Floppy
end
device pnp 4e.1 off # Parport
end
device pnp 4e.2 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 4e.3 on # COM2
io 0x60 = 0x2f8
irq 0x70 = 3
irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq
end
device pnp 4e.5 on # Keyboard+Mouse
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
irq 0xf0 = 0x82 # HW accel A20.
end
device pnp 4e.7 on # GPIO1, GAME, MIDI
io 0x62 = 0x330
irq 0x70 = 9
end
device pnp 4e.8 on # GPIO2
# all default
end
device pnp 4e.9 on # GPIO3/4
irq 0x30 = 0x03 # does this work?
irq 0xf0 = 0xfb # set inputs/outputs
irq 0xf1 = 0x66
end
device pnp 4e.a on # ACPI
end
device pnp 4e.b on # HWM
io 0x60 = 0x290
irq 0x70 = 0
end
end
end
device pci 1f.1 on end # IDE
device pci 1f.2 on end # SATA
device pci 1f.3 on end # SMBus
#device pci 1f.4 off end # Realtek ID Codec
end
end
end

29
src/mainboard/ibase/mb899/dmi.h Normal file
View File

@ -0,0 +1,29 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define DMI_TABLE_SIZE 0x55
static u8 dmi_table[DMI_TABLE_SIZE] = {
0x5f, 0x53, 0x4d, 0x5f, 0x29, 0x1f, 0x02, 0x03, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x5f, 0x44, 0x4d, 0x49, 0x5f, 0x61, 0x35, 0x00, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00,
0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde, 0xcb, 0x7f, 0x00, 0x00,
0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x73, 0x20,
0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f, 0x31, 0x33, 0x2f, 0x32,
0x30, 0x30, 0x38, 0x00, 0x00
};

50
src/mainboard/ibase/mb899/dsdt.asl Normal file
View File

@ -0,0 +1,50 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x02, // DSDT revision: ACPI v2.0
"COREv2", // OEM id
"COREBOOT", // OEM table id
0x20090419 // OEM revision
)
{
// Some generic macros
#include "acpi/platform.asl"
// global NVS and variables
#include "../../../southbridge/intel/i82801gx/acpi/globalnvs.asl"
// General Purpose Events
//#include "acpi/gpe.asl"
//#include "acpi/thermal.asl"
Scope (\_SB) {
Device (PCI0)
{
#include "../../../northbridge/intel/i945/acpi/i945.asl"
#include "../../../southbridge/intel/i82801gx/acpi/ich7.asl"
}
}
/* Chipset specific sleep states */
#include "../../../southbridge/intel/i82801gx/acpi/sleepstates.asl"
}

165
src/mainboard/ibase/mb899/fadt.c Normal file
View File

@ -0,0 +1,165 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <string.h>
#include <device/pci.h>
#include <arch/acpi.h>
/* FIXME: This needs to go into a separate .h file
* to be included by the ich7 smi handler, ich7 smi init
* code and the mainboard fadt.
*/
#define APM_CNT 0xb2
#define CST_CONTROL 0x85
#define PST_CONTROL 0x80
#define ACPI_DISABLE 0x1e
#define ACPI_ENABLE 0xe1
#define GNVS_UPDATE 0xea
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
{
acpi_header_t *header = &(fadt->header);
u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe;
memset((void *) fadt, 0, sizeof(acpi_fadt_t));
memcpy(header->signature, "FACP", 4);
header->length = sizeof(acpi_fadt_t);
header->revision = 3;
memcpy(header->oem_id, "CORE ", 6);
memcpy(header->oem_table_id, "COREBOOT", 8);
memcpy(header->asl_compiler_id, "CORE", 4);
header->asl_compiler_revision = 1;
fadt->firmware_ctrl = (unsigned long) facs;
fadt->dsdt = (unsigned long) dsdt;
fadt->model = 1;
fadt->preferred_pm_profile = PM_MOBILE;
fadt->sci_int = 0x9;
fadt->smi_cmd = APM_CNT;
fadt->acpi_enable = ACPI_ENABLE;
fadt->acpi_disable = ACPI_DISABLE;
fadt->s4bios_req = 0x0;
fadt->pstate_cnt = PST_CONTROL;
fadt->pm1a_evt_blk = pmbase;
fadt->pm1b_evt_blk = 0x0;
fadt->pm1a_cnt_blk = pmbase + 0x4;
fadt->pm1b_cnt_blk = 0x0;
fadt->pm2_cnt_blk = pmbase + 0x20;
fadt->pm_tmr_blk = pmbase + 0x8;
fadt->gpe0_blk = pmbase + 0x28;
fadt->gpe1_blk = 0;
fadt->pm1_evt_len = 4;
fadt->pm1_cnt_len = 2;
// XXX: pm2_cnt_len is probably wrong. find out right value (hint: it's != 0)
fadt->pm2_cnt_len = 2;
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 8;
fadt->gpe1_blk_len = 0;
fadt->gpe1_base = 0;
fadt->cst_cnt = CST_CONTROL;
fadt->p_lvl2_lat = 1;
fadt->p_lvl3_lat = 85;
fadt->flush_size = 1024;
fadt->flush_stride = 16;
fadt->duty_offset = 1;
fadt->duty_width = 0;
fadt->day_alrm = 0xd;
fadt->mon_alrm = 0x00;
fadt->century = 0x00;
fadt->iapc_boot_arch = 0x03;
fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
fadt->reset_reg.space_id = 0;
fadt->reset_reg.bit_width = 0;
fadt->reset_reg.bit_offset = 0;
fadt->reset_reg.resv = 0;
fadt->reset_reg.addrl = 0x0;
fadt->reset_reg.addrh = 0x0;
fadt->reset_value = 0;
fadt->x_firmware_ctl_l = (unsigned long)facs;
fadt->x_firmware_ctl_h = 0;
fadt->x_dsdt_l = (unsigned long)dsdt;
fadt->x_dsdt_h = 0;
fadt->x_pm1a_evt_blk.space_id = 1;
fadt->x_pm1a_evt_blk.bit_width = 32;
fadt->x_pm1a_evt_blk.bit_offset = 0;
fadt->x_pm1a_evt_blk.resv = 0;
fadt->x_pm1a_evt_blk.addrl = pmbase;
fadt->x_pm1a_evt_blk.addrh = 0x0;
fadt->x_pm1b_evt_blk.space_id = 1;
fadt->x_pm1b_evt_blk.bit_width = 0;
fadt->x_pm1b_evt_blk.bit_offset = 0;
fadt->x_pm1b_evt_blk.resv = 0;
fadt->x_pm1b_evt_blk.addrl = 0x0;
fadt->x_pm1b_evt_blk.addrh = 0x0;
fadt->x_pm1a_cnt_blk.space_id = 1;
fadt->x_pm1a_cnt_blk.bit_width = 16;
fadt->x_pm1a_cnt_blk.bit_offset = 0;
fadt->x_pm1a_cnt_blk.resv = 0;
fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
fadt->x_pm1a_cnt_blk.addrh = 0x0;
fadt->x_pm1b_cnt_blk.space_id = 1;
fadt->x_pm1b_cnt_blk.bit_width = 0;
fadt->x_pm1b_cnt_blk.bit_offset = 0;
fadt->x_pm1b_cnt_blk.resv = 0;
fadt->x_pm1b_cnt_blk.addrl = 0x0;
fadt->x_pm1b_cnt_blk.addrh = 0x0;
fadt->x_pm2_cnt_blk.space_id = 1;
fadt->x_pm2_cnt_blk.bit_width = 8;
fadt->x_pm2_cnt_blk.bit_offset = 0;
fadt->x_pm2_cnt_blk.resv = 0;
fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20;
fadt->x_pm2_cnt_blk.addrh = 0x0;
fadt->x_pm_tmr_blk.space_id = 1;
fadt->x_pm_tmr_blk.bit_width = 32;
fadt->x_pm_tmr_blk.bit_offset = 0;
fadt->x_pm_tmr_blk.resv = 0;
fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
fadt->x_pm_tmr_blk.addrh = 0x0;
fadt->x_gpe0_blk.space_id = 1;
fadt->x_gpe0_blk.bit_width = 64;
fadt->x_gpe0_blk.bit_offset = 0;
fadt->x_gpe0_blk.resv = 0;
fadt->x_gpe0_blk.addrl = pmbase + 0x28;
fadt->x_gpe0_blk.addrh = 0x0;
fadt->x_gpe1_blk.space_id = 1;
fadt->x_gpe1_blk.bit_width = 0;
fadt->x_gpe1_blk.bit_offset = 0;
fadt->x_gpe1_blk.resv = 0;
fadt->x_gpe1_blk.addrl = 0x0;
fadt->x_gpe1_blk.addrh = 0x0;
header->checksum =
acpi_checksum((void *) fadt, header->length);
}

61
src/mainboard/ibase/mb899/irq_tables.c Normal file
View File

@ -0,0 +1,61 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2008 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/pirq_routing.h>
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
0x00, /* Where the interrupt router lies (bus) */
(0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */
0, /* IRQs devoted exclusively to PCI usage */
0x8086, /* Vendor */
0x27b9, /* Device */
0, /* miniport */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0xf, /* u8 checksum. */
{
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x01<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe?
{0x00,(0x02<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA
{0x00,(0x1e<<3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge
{0x00,(0x1f<<3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC
{0x00,(0x1d<<3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1
{0x00,(0x1b<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device
{0x00,(0x1c<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge
{0x04,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire
{0x04,(0x01<<3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge
{0x04,(0x02<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
{0x04,(0x03<<3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
{0x04,(0x04<<3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
{0x04,(0x05<<3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
{0x04,(0x06<<3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
{0x04,(0x09<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
{0x01,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet Marvell 88E8053
{0x02,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
{0x03,(0x00<<3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr);
}

243
src/mainboard/ibase/mb899/mainboard.c Normal file
View File

@ -0,0 +1,243 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <types.h>
#include <device/device.h>
#include <console/console.h>
#include <boot/tables.h>
#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
#include <x86emu/x86emu.h>
#endif
#include <pc80/mc146818rtc.h>
#include <arch/io.h>
#include <arch/coreboot_tables.h>
#include "chip.h"
int add_mainboard_resources(struct lb_memory *mem)
{
return add_northbridge_resources(mem);
}
#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
static int int15_handler(void)
{
#define BOOT_DISPLAY_DEFAULT 0
#define BOOT_DISPLAY_CRT (1 << 0)
#define BOOT_DISPLAY_TV (1 << 1)
#define BOOT_DISPLAY_EFP (1 << 2)
#define BOOT_DISPLAY_LCD (1 << 3)
#define BOOT_DISPLAY_CRT2 (1 << 4)
#define BOOT_DISPLAY_TV2 (1 << 5)
#define BOOT_DISPLAY_EFP2 (1 << 6)
#define BOOT_DISPLAY_LCD2 (1 << 7)
printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
__func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
switch (M.x86.R_AX) {
case 0x5f35: /* Boot Display */
M.x86.R_AX = 0x005f; // Success
M.x86.R_CL = BOOT_DISPLAY_DEFAULT;
break;
case 0x5f40: /* Boot Panel Type */
// M.x86.R_AX = 0x015f; // Supported but failed
M.x86.R_AX = 0x005f; // Success
M.x86.R_CL = 3; // Display ID
break;
default:
/* Interrupt was not handled */
return 0;
}
/* Interrupt handled */
return 1;
}
static void int15_install(void)
{
typedef int (* yabel_handleIntFunc)(void);
extern yabel_handleIntFunc yabel_intFuncArray[256];
yabel_intFuncArray[0x15] = int15_handler;
}
#endif
/* Hardware Monitor */
static u16 hwm_base = 0x290;
static void hwm_write(u8 reg, u8 value)
{
outb(reg, hwm_base + 0x05);
outb(value, hwm_base + 0x06);
}
static void hwm_bank(u8 bank)
{
hwm_write(0x4e, bank);
}
#define FAN_CRUISE_CONTROL_DISABLED 0
#define FAN_CRUISE_CONTROL_SPEED 1
#define FAN_CRUISE_CONTROL_THERMAL 2
#define FAN_SPEED_5625 0
//#define FAN_TEMPERATURE_30DEGC 0
struct fan_speed {
u8 fan_in;
u16 fan_speed;
};
// FANIN Target Speed Register
// FANIN = 337500 / RPM
struct fan_speed fan_speeds[] = {
{ 0x3c, 5625 }, { 0x41, 5192 }, { 0x47, 4753 }, { 0x4e, 4326 },
{ 0x56, 3924 }, { 0x5f, 3552 }, { 0x69, 3214 }, { 0x74, 2909 },
{ 0x80, 2636 }, { 0x8d, 2393 }, { 0x9b, 2177 }, { 0xaa, 1985 },
{ 0xba, 1814 }, { 0xcb, 1662 }, { 0xdd, 1527 }, { 0xf0, 1406 }
};
struct temperature {
u8 deg_celsius;
u8 deg_fahrenheit;
};
struct temperature temperatures[] = {
{ 30, 86 }, { 33, 91 }, { 36, 96 }, { 39, 102 },
{ 42, 107 }, { 45, 113 }, { 48, 118 }, { 51, 123 },
{ 54, 129 }, { 57, 134 }, { 60, 140 }, { 63, 145 },
{ 66, 150 }, { 69, 156 }, { 72, 161 }, { 75, 167 }
};
static void hwm_setup(void)
{
int cpufan_control = 0, sysfan_control = 0;
int cpufan_speed = 0, sysfan_speed = 0;
int cpufan_temperature = 0, sysfan_temperature = 0;
if (get_option(&cpufan_control, "cpufan_cruise_control") < 0)
cpufan_control = FAN_CRUISE_CONTROL_DISABLED;
if (get_option(&cpufan_speed, "cpufan_speed") < 0)
cpufan_speed = FAN_SPEED_5625;
//if (get_option(&cpufan_temperature, "cpufan_temperature") < 0)
// cpufan_temperature = FAN_TEMPERATURE_30DEGC;
if (get_option(&sysfan_control, "sysfan_cruise_control") < 0)
sysfan_control = FAN_CRUISE_CONTROL_DISABLED;
if (get_option(&sysfan_speed, "sysfan_speed") < 0)
sysfan_speed = FAN_SPEED_5625;
//if (get_option(&sysfan_temperature, "sysfan_temperature") < 0)
// sysfan_temperature = FAN_TEMPERATURE_30DEGC;
// hwm_write(0x31, 0x20); // AVCC high limit
// hwm_write(0x34, 0x06); // VIN2 low limit
hwm_bank(0);
hwm_write(0x59, 0x20); // Diode Selection
hwm_write(0x5d, 0x0f); // All Sensors Diode, not Thermistor
hwm_bank(4);
hwm_write(0x54, 0xf1); // SYSTIN temperature offset
hwm_write(0x55, 0x19); // CPUTIN temperature offset
hwm_write(0x56, 0xfc); // AUXTIN temperature offset
hwm_bank(0x80); // Default
u8 fan_config = 0;
// 00 FANOUT is Manual Mode
// 01 FANOUT is Thermal Cruise Mode
// 10 FANOUT is Fan Speed Cruise Mode
switch (cpufan_control) {
case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 4); break;
case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 4); break;
}
switch (sysfan_control) {
case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 2); break;
case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 2); break;
}
// This register must be written first
hwm_write(0x04, fan_config);
switch (cpufan_control) {
case FAN_CRUISE_CONTROL_SPEED:
printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to %d RPM\n",
fan_speeds[cpufan_speed].fan_speed);
hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); // CPUFANIN target speed
break;
case FAN_CRUISE_CONTROL_THERMAL:
printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n",
temperatures[cpufan_temperature].deg_celsius,
temperatures[cpufan_temperature].deg_fahrenheit);
hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); // CPUFANIN target temperature
break;
}
switch (sysfan_control) {
case FAN_CRUISE_CONTROL_SPEED:
printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to %d RPM\n",
fan_speeds[sysfan_speed].fan_speed);
hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); // SYSFANIN target speed
break;
case FAN_CRUISE_CONTROL_THERMAL:
printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n",
temperatures[sysfan_temperature].deg_celsius,
temperatures[sysfan_temperature].deg_fahrenheit);
hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); // SYSFANIN target temperature
break;
}
hwm_write(0x0e, 0x02); // Fan Output Step Down Time
hwm_write(0x0f, 0x02); // Fan Output Step Up Time
hwm_write(0x47, 0xaf); // FAN divisor register
hwm_write(0x4b, 0x84); // AUXFANIN speed divisor
hwm_write(0x40, 0x01); // Init, but no SMI#
}
/* Audio Setup */
extern u32 * cim_verb_data;
extern u32 cim_verb_data_size;
static void verb_setup(void)
{
// Default VERB is fine on this mainboard.
cim_verb_data = NULL;
cim_verb_data_size = 0;
}
// mainboard_enable is executed as first thing after
// enumerate_buses().
static void mainboard_enable(device_t dev)
{
#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
/* Install custom int15 handler for VGA OPROM */
int15_install();
#endif
verb_setup();
hwm_setup();
}
struct chip_operations mainboard_ops = {
CHIP_NAME("iBASE MB899 Mainboard")
.enable_dev = mainboard_enable,
};

52
src/mainboard/ibase/mb899/mainboard_smi.c Normal file
View File

@ -0,0 +1,52 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/io.h>
#include <arch/romcc_io.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include "../../../southbridge/intel/i82801gx/i82801gx_nvs.h"
/* The southbridge SMI handler checks whether gnvs has a
* valid pointer before calling the trap handler
*/
extern global_nvs_t *gnvs;
int mainboard_io_trap_handler(int smif)
{
switch (smif) {
case 0x99:
printk(BIOS_DEBUG, "Sample\n");
gnvs->smif = 0;
break;
default:
return 0;
}
/* On success, the IO Trap Handler returns 0
* On failure, the IO Trap Handler returns a value != 0
*
* For now, we force the return value to 0 and log all traps to
* see what's going on.
*/
//gnvs->smif = 0;
return 1;
}

183
src/mainboard/ibase/mb899/mptable.c Normal file
View File

@ -0,0 +1,183 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2008 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <device/device.h>
#include <device/pci.h>
#include <console/console.h>
#include <arch/smp/mpspec.h>
#include <string.h>
#include <stdint.h>
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "COREBOOT";
static const char productid[12] = "MB899 ";
struct mp_config_table *mc;
struct device *riser = NULL, *firewire = NULL;
int i;
int max_pci_bus, firewire_bus = 0, riser_bus = 0, isa_bus;
int ioapic_id;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
memset(mc, 0, sizeof(*mc));
memcpy(mc->mpc_signature, sig, sizeof(sig));
mc->mpc_length = sizeof(*mc); /* initially just the header */
mc->mpc_spec = 0x04;
mc->mpc_checksum = 0; /* not yet computed */
memcpy(mc->mpc_oem, oem, sizeof(oem));
memcpy(mc->mpc_productid, productid, sizeof(productid));
mc->mpc_oemptr = 0;
mc->mpc_oemsize = 0;
mc->mpc_entry_count = 0; /* No entries yet... */
mc->mpc_lapic = LAPIC_ADDR;
mc->mpe_length = 0;
mc->mpe_checksum = 0;
mc->reserved = 0;
smp_write_processors(mc);
max_pci_bus=0;
firewire = dev_find_device(0x104c, 0x8023, 0);
if (firewire) {
firewire_bus = firewire->bus->secondary;
printk(BIOS_SPEW, "Firewire device is on bus %x\n",
firewire_bus);
max_pci_bus = firewire_bus;
}
// If a riser card is used, this riser is detected on bus 4, so its secondary bus is the
// highest bus number on the pci bus.
riser = dev_find_device(0x3388, 0x0021, 0);
if (!riser)
riser = dev_find_device(0x3388, 0x0022, 0);
if (riser) {
riser_bus = riser->link[0].secondary;
printk(BIOS_SPEW, "Riser bus is %x\n", riser_bus);
max_pci_bus = riser_bus;
}
/* ISA bus follows */
isa_bus = max_pci_bus + 1;
/* Bus: Bus ID Type */
for (i=0; i <= max_pci_bus; i++)
smp_write_bus(mc, i, "PCI ");
smp_write_bus(mc, isa_bus, "ISA ");
/* I/O APICs: APIC ID Version State Address */
ioapic_id = 2;
smp_write_ioapic(mc, ioapic_id, 0x20, 0xfec00000);
/* Legacy Interrupts */
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, ioapic_id, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x1, ioapic_id, 0x1);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, ioapic_id, 0x2);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x3, ioapic_id, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x4, ioapic_id, 0x4);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x8, ioapic_id, 0x8);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x9, ioapic_id, 0x9);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xa, ioapic_id, 0xa);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xb, ioapic_id, 0xb);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xc, ioapic_id, 0xc);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xd, ioapic_id, 0xd);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xe, ioapic_id, 0xe);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xf, ioapic_id, 0xf);
/* Builtin devices on Bus 0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x4, ioapic_id, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, ioapic_id, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, ioapic_id, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, ioapic_id, 0x17);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, ioapic_id, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, ioapic_id, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, ioapic_id, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, ioapic_id, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, ioapic_id, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, ioapic_id, 0x11);
/* Internal PCI bus (Firewire, PCI slot) */
if (firewire) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, firewire_bus, 0x0, ioapic_id, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, firewire_bus, 0x4, ioapic_id, 0x14);
}
if (riser) {
/* Old riser card */
// riser slot top 5:8.0
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x20, ioapic_id, 0x14);
// riser slot middle 5:9.0
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x24, ioapic_id, 0x15);
// riser slot bottom 5:a.0
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x28, ioapic_id, 0x16);
/* New Riser Card */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x30, ioapic_id, 0x14);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x34, ioapic_id, 0x15);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x38, ioapic_id, 0x16);
}
/* PCIe slot */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, ioapic_id, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1, ioapic_id, 0x11);
/* Onboard Ethernet */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x0, ioapic_id, 0x10);
/* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0);
smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1);
/* Compute the checksums */
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
/* MP table generation in coreboot is not very well designed;
* One of the issues is that it knows nothing about Virtual
* Wire mode, which everyone uses since a decade or so. This
* function fixes up our floating table. This spares us doing
* a half-baked fix of adding a new parameter to 200+ calls
* to smp_write_floating_table()
*/
static void fixup_virtual_wire(void *v)
{
struct intel_mp_floating *mf = v;
mf->mpf_checksum = 0;
mf->mpf_feature2 = MP_FEATURE_VIRTUALWIRE;
mf->mpf_checksum = smp_compute_checksum(mf, mf->mpf_length*16);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr);
fixup_virtual_wire(v);
return (unsigned long)smp_write_config_table(v);
}

382
src/mainboard/ibase/mb899/romstage.c Normal file
View File

@ -0,0 +1,382 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2010 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
// __PRE_RAM__ means: use "unsigned" for device, not a struct.
/* Configuration of the i945 driver */
#define CHIPSET_I945GM 1
//#define OVERRIDE_CLOCK_DISABLE 1
#define CHANNEL_XOR_RANDOMIZATION 1
#include <stdint.h>
#include <string.h>
#include <arch/io.h>
#include <arch/romcc_io.h>
#include <device/pci_def.h>
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include "superio/winbond/w83627ehg/w83627ehg.h"
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include <console/console.h>
#include <cpu/x86/bist.h>
#if CONFIG_USBDEBUG
#define DBGP_DEFAULT 1
#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
#include "pc80/usbdebug_serial.c"
#endif
#include "lib/ramtest.c"
#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c"
#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
#include "northbridge/intel/i945/udelay.c"
#define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
#include "southbridge/intel/i82801gx/i82801gx.h"
static void setup_ich7_gpios(void)
{
printk(BIOS_DEBUG, " GPIOS...");
/* General Registers */
outl(0x1f1ff7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
outl(0xe0e8efc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
outl(0xebffeeff, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
/* Output Control Registers */
outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */
/* Input Control Registers */
outl(0x00002180, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
outl(0x000100ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */
outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */
outl(0x00010035, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */
}
#include "northbridge/intel/i945/early_init.c"
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
#include "northbridge/intel/i945/raminit.h"
#include "northbridge/intel/i945/raminit.c"
#include "northbridge/intel/i945/errata.c"
#include "northbridge/intel/i945/debug.c"
static void ich7_enable_lpc(void)
{
// Enable Serial IRQ
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
// Set COM1/COM2 decode range
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
// Enable COM1/COM2/KBD/SuperIO1+2
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b);
// Enable HWM at 0x290
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0291);
// io 0x300 decode
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301);
}
/* This box has one superio
* Also set up the GPIOs from the beginning. This is the "no schematic
* but safe anyways" method.
*/
static void early_superio_config_w83627ehg(void)
{
device_t dev;
dev=PNP_DEV(0x4e, W83627EHG_SP1);
pnp_enter_ext_func_mode(dev);
pnp_write_config(dev, 0x24, 0xc4); // PNPCSV
pnp_write_config(dev, 0x29, 0x01); // GPIO settings
pnp_write_config(dev, 0x2a, 0x40); // GPIO settings should be fc but gets set to 02
pnp_write_config(dev, 0x2b, 0xc0); // GPIO settings?
pnp_write_config(dev, 0x2c, 0x03); // GPIO settings?
pnp_write_config(dev, 0x2d, 0x20); // GPIO settings?
dev=PNP_DEV(0x4e, W83627EHG_SP1);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8);
pnp_set_irq(dev, PNP_IDX_IRQ0, 4);
pnp_set_enable(dev, 1);
dev=PNP_DEV(0x4e, W83627EHG_SP2);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8);
pnp_set_irq(dev, PNP_IDX_IRQ0, 3);
// pnp_write_config(dev, 0xf1, 4); // IRMODE0
pnp_set_enable(dev, 1);
dev=PNP_DEV(0x4e, W83627EHG_KBC); // Keyboard
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x60);
pnp_set_iobase(dev, PNP_IDX_IO1, 0x64);
//pnp_write_config(dev, 0xf0, 0x82);
pnp_set_enable(dev, 1);
dev=PNP_DEV(0x4e, W83627EHG_GPIO2);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 1); // Just enable it
dev=PNP_DEV(0x4e, W83627EHG_GPIO3);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output
pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0
pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient
dev=PNP_DEV(0x4e, W83627EHG_FDC);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
dev=PNP_DEV(0x4e, W83627EHG_PP);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
/* Enable HWM */
dev=PNP_DEV(0x4e, W83627EHG_HWM);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00);
pnp_set_enable(dev, 1);
pnp_exit_ext_func_mode(dev);
}
static void rcba_config(void)
{
/* Set up virtual channel 0 */
//RCBA32(0x0014) = 0x80000001;
//RCBA32(0x001c) = 0x03128010;
/* Device 1f interrupt pin register */
RCBA32(0x3100) = 0x00042210;
/* Device 1d interrupt pin register */
RCBA32(0x310c) = 0x00214321;
/* dev irq route register */
RCBA16(0x3140) = 0x0132;
RCBA16(0x3142) = 0x0146;
RCBA16(0x3144) = 0x0237;
RCBA16(0x3146) = 0x3201;
RCBA16(0x3148) = 0x0146;
/* Enable IOAPIC */
RCBA8(0x31ff) = 0x03;
/* Enable upper 128bytes of CMOS */
RCBA32(0x3400) = (1 << 2);
/* Enable PCIe Root Port Clock Gate */
// RCBA32(0x341c) = 0x00000001;
}
static void early_ich7_init(void)
{
uint8_t reg8;
uint32_t reg32;
// program secondary mlt XXX byte?
pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
// reset rtc power status
reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
reg8 &= ~(1 << 2);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
// usb transient disconnect
reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
reg8 |= (3 << 0);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
reg32 |= (1 << 29) | (1 << 17);
pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
reg32 |= (1 << 31) | (1 << 27);
pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
RCBA32(0x0088) = 0x0011d000;
RCBA16(0x01fc) = 0x060f;
RCBA32(0x01f4) = 0x86000040;
RCBA32(0x0214) = 0x10030549;
RCBA32(0x0218) = 0x00020504;
RCBA8(0x0220) = 0xc5;
reg32 = RCBA32(0x3410);
reg32 |= (1 << 6);
RCBA32(0x3410) = reg32;
reg32 = RCBA32(0x3430);
reg32 &= ~(3 << 0);
reg32 |= (1 << 0);
RCBA32(0x3430) = reg32;
RCBA32(0x3418) |= (1 << 0);
RCBA16(0x0200) = 0x2008;
RCBA8(0x2027) = 0x0d;
RCBA16(0x3e08) |= (1 << 7);
RCBA16(0x3e48) |= (1 << 7);
RCBA32(0x3e0e) |= (1 << 7);
RCBA32(0x3e4e) |= (1 << 7);
// next step only on ich7m b0 and later:
reg32 = RCBA32(0x2034);
reg32 &= ~(0x0f << 16);
reg32 |= (5 << 16);
RCBA32(0x2034) = reg32;
}
#include <cbmem.h>
// Now, this needs to be included because it relies on the symbol
// __PRE_RAM__ being set during CAR stage (in order to compile the
// BSS free versions of the functions). Either rewrite the code
// to be always BSS free, or invent a flag that's better suited than
// __PRE_RAM__ to determine whether we're in ram init stage (stage 1)
//
#include "lib/cbmem.c"
void main(unsigned long bist)
{
u32 reg32;
int boot_mode = 0;
if (bist == 0) {
enable_lapic();
}
ich7_enable_lpc();
early_superio_config_w83627ehg();
/* Set up the console */
uart_init();
#if CONFIG_USBDEBUG
i82801gx_enable_usbdebug(DBGP_DEFAULT);
early_usbdebug_init();
#endif
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
outb(0x6, 0xcf9);
while (1) asm("hlt");
}
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
i945_early_initialization();
/* Read PM1_CNT */
reg32 = inl(DEFAULT_PMBASE + 0x04);
printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
if (((reg32 >> 10) & 7) == 5) {
#if CONFIG_HAVE_ACPI_RESUME
printk(BIOS_DEBUG, "Resume from S3 detected.\n");
boot_mode = 2;
/* Clear SLP_TYPE. This will break stage2 but
* we care for that when we get there.
*/
outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
#else
printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
#endif
}
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
dump_spd_registers();
#endif
sdram_initialize(boot_mode);
/* Perform some initialization that must run before stage2 */
early_ich7_init();
/* This should probably go away. Until now it is required
* and mainboard specific
*/
rcba_config();
/* Chipset Errata! */
fixup_i945_errata();
/* Initialize the internal PCIe links before we go into stage2 */
i945_late_initialization();
#if !CONFIG_HAVE_ACPI_RESUME
#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
#if CONFIG_DEBUG_RAM_SETUP
sdram_dump_mchbar_registers();
#endif
{
/* This will not work if TSEG is in place! */
u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
ram_check(0x00000000, 0x000a0000);
//ram_check(0x00100000, tom);
}
#endif
#endif
quick_ram_check();
MCHBAR16(SSKPD) = 0xCAFE;
#if CONFIG_HAVE_ACPI_RESUME
/* Start address of high memory tables */
unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE;
/* If there is no high memory area, we didn't boot before, so
* this is not a resume. In that case we just create the cbmem toc.
*/
if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) {
void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
/* copy 1MB - 64K to high tables ram_base to prevent memory corruption
* through stage 2. We could keep stuff like stack and heap in high tables
* memory completely, but that's a wonderful clean up task for another
* day.
*/
if (resume_backup_memory)
memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
/* Magic for S3 resume */
pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
}
#endif
}

49
src/mainboard/ibase/mb899/rtl8168.c Normal file
View File

@ -0,0 +1,49 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* This code should work for all ICH* southbridges with a NIC. */
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
static void nic_init(struct device *dev)
{
printk(BIOS_DEBUG, "Initializing 88E8053 Gigabit Ethernet\n");
// Nothing to do yet, but this has to be here to keep
// coreboot from trying to execute an option ROM.
}
static struct device_operations nic_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = nic_init,
.scan_bus = 0,
};
static const struct pci_driver rtl8169_nic __pci_driver = {
.ops = &nic_ops,
.vendor = 0x11ab,
.device = 0x4362,
};