coreboot: add Volteer template files
Add template files for making a new barebones-copy of Volteer. BUG=b:147483699 BRANCH=None TEST=N/A Change-Id: I8cc69b8ce7dbc6809de058019bdc466a060069e7 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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##
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## This file is part of the coreboot project.
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##
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## Copyright 2020 Google LLC
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2020 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef __VARIANT_EC_H__
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#define __VARIANT_EC_H__
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#include <baseboard/ec.h>
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#endif
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2020 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef VARIANT_GPIO_H
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#define VARIANT_GPIO_H
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#include <baseboard/gpio.h>
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/* Memory configuration board straps */
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/* Copied from baseboard and may need to change for the new variant. */
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#define GPIO_MEM_CONFIG_0 GPP_C12
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#define GPIO_MEM_CONFIG_1 GPP_C15
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#define GPIO_MEM_CONFIG_2 GPP_C14
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#define GPIO_MEM_CONFIG_3 GPP_D15
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#endif
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chip soc/intel/tigerlake
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device domain 0 on
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end
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end
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