Jetway NF81-T56N-LF [2/2]: actually implement mainboard support.
Step 2: change the Persimmon code to adapt it to the new board's hardware.
The NF81-T56N-LF is a IPC form factor embedded board:
- AMD Fusion G-T56N (1.65 GHz dual core) APU
- 2x SO-DIMM sockets for DDR3 800-1066 SDRAM (Fixed at 1.5V)
- VGA and LVDS (via Analogix ANX3110)
- AMD A55E (Hudson-E1) southbridge
- 6x USB 2.0/1.1 ports
- 5x SATA3 6Gb/s, 1x mSATA socket
- 6-Channel HD Audio (via VIA VT1705)
- PCI and ISA (via ITE IT8888)??
- NEC uPD78F0532 microcontroller on I2C ("SEMA")??
- 2x RJ45 GbE (via Realtek RTL8111E x2)
- Fintek F71869AD Super I/O
- PS/2 KB/MS port
- RS232 header (via Unisonic UTC 75232 RS232 driver/receiver)
- GPIO header
- CIR header
- 1x MXIC MX25L1606E (SO8, soldered) 16 Mbit SPI flash (BIOS)
Note: MX25L1606E is 16Mbit, 8bits in a byte, so 2MB. Jetway *lies*
claiming the SPI flash is 16MB. They also use red pen over the chip
so you wont see this deceit.
Change-Id: I03ccc58bc782e800aeef0d19679ce060277b0c04
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/4801
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Edward O'Callaghan
Alexandru Gagniuc
parent
4726a87c9a
commit
6e56de3d20
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@ -11,6 +11,8 @@ config BOARD_JETWAY_J7F4K1G5D
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bool "J7F4K1G5D"
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config BOARD_JETWAY_PA78VM5
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bool "PA78VM5 (Fam10)"
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config BOARD_JETWAY_NF81_T56N_LF
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bool "NF81_T56N_LF"
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endchoice
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@ -18,6 +20,7 @@ source "src/mainboard/jetway/j7f2/Kconfig"
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source "src/mainboard/jetway/j7f4k1g2e/Kconfig"
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source "src/mainboard/jetway/j7f4k1g5d/Kconfig"
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source "src/mainboard/jetway/pa78vm5/Kconfig"
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source "src/mainboard/jetway/nf81-t56n-lf/Kconfig"
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config MAINBOARD_VENDOR
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string
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@ -2,6 +2,7 @@
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2011 Advanced Micro Devices, Inc.
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# Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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@ -17,7 +18,7 @@
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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if BOARD_AMD_PERSIMMON
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if BOARD_JETWAY_NF81_T56N_LF
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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@ -25,22 +26,23 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select CPU_AMD_AGESA_FAMILY14
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select NORTHBRIDGE_AMD_AGESA_FAMILY14
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select SOUTHBRIDGE_AMD_CIMX_SB800
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select SUPERIO_FINTEK_F81865F
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select SUPERIO_FINTEK_F71869AD
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select HAVE_OPTION_TABLE
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select HAVE_PIRQ_TABLE
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select HAVE_MP_TABLE
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select HAVE_ACPI_RESUME
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# FIXME: Disable S3 for now. Enable by default once stabilised.
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# select HAVE_ACPI_RESUME
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select SB_HT_CHAIN_UNITID_OFFSET_ONLY
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select LIFT_BSP_APIC_ID
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select SERIAL_CPU_INIT
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select AMDMCT
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select HAVE_ACPI_TABLES
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select BOARD_ROMSIZE_KB_4096
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select BOARD_ROMSIZE_KB_2048
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select GFXUMA
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config MAINBOARD_DIR
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string
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default amd/persimmon
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default jetway/nf81-t56n-lf
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config APIC_ID_OFFSET
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hex
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@ -48,7 +50,7 @@ config APIC_ID_OFFSET
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config MAINBOARD_PART_NUMBER
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string
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default "Persimmon"
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default "NF81-T56N-LF"
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config HW_MEM_HOLE_SIZEK
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hex
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@ -101,7 +103,7 @@ config VGA_BIOS
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config VGA_BIOS_ID
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string
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default "1002,9802"
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default "1002,9806" # FUSION_G_T56N
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config SB800_AHCI_ROM
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bool
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@ -111,4 +113,4 @@ config DRIVERS_PS2_KEYBOARD
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bool
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default n
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endif # BOARD_AMD_PERSIMMON
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endif # BOARD_JETWAY_NF81_T56N_LF
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@ -1,5 +1,6 @@
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Board name: DBFT1-00-EVAL-KT (Persimmon)
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Category: eval
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Board URL: http://www.jetway.com.tw/jw/ipcboard_view.asp?productid=822&proname=NF81-T56N-LF
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Category: Mini-ITX
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ROM package: SOIC8
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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@ -2,6 +2,7 @@
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2011 Advanced Micro Devices, Inc.
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# Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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@ -29,7 +30,8 @@ chip northbridge/amd/agesa/family14/root_complex
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chip northbridge/amd/agesa/family14 # PCI side of HT root complex
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device pci 0.0 on end # Root Complex
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device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456]
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device pci 4.0 on end # PCIE P2P bridge on-board NIC
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# device pci 1.1 on end # Internal Audio P2P bridge 0x1314
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device pci 4.0 off end
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device pci 5.0 off end # PCIE P2P bridge
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device pci 6.0 on end # PCIE P2P bridge PCIe slot
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device pci 7.0 off end # PCIE P2P bridge
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@ -50,47 +52,64 @@ chip northbridge/amd/agesa/family14/root_complex
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device i2c 51 on end
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end
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end # SM
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device pci 14.1 on end # IDE 0x439c
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device pci 14.1 off end # IDE 0x439c
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device pci 14.2 on end # HDA 0x4383
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device pci 14.3 on # LPC 0x439d
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chip superio/fintek/f81865f
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device pnp 4e.0 off # Floppy
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chip superio/fintek/f71869ad
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# XXX: 4e is the default index port and .xy is the
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# LDN indexing the pnp_info array found in the superio.c
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# NB: Jetway board changes the default (0x4e) index port to (0x2e) by pin 124,
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# see page 18 from Fintek F71869 V1.1 datasheet.
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device pnp 2e.00 off # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 4e.3 off end # Parallel Port
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device pnp 4e.4 off end # Hardware Monitor
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device pnp 4e.5 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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end
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device pnp 4e.6 off end # GPIO
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device pnp 4e.a off end # PME
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device pnp 4e.10 on # COM1
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device pnp 2e.01 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 4e.11 on # COM2
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# COM2 not physically wired on board.
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device pnp 2e.02 off # COM2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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end # f81865f
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device pnp 2e.03 off # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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drq 0x74 = 3
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end
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device pnp 2e.04 on # Hardware Monitor
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io 0x60 = 0x295
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irq 0x70 = 0
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end
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device pnp 2e.05 on # KBC
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io 0x60 = 0x060
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irq 0x70 = 1 # Keyboard IRQ
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irq 0x72 = 12 # Mouse IRQ
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end
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device pnp 2e.06 off end # GPIO
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# TODO: Verify BSEL register content with vendor BIOS using
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# $ sudo isadump 0x4e 0x4f 0x7
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# which select logical device (LDN) 7. Then read that we have in 0x27, bit1
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device pnp 2e.07 on end # BSEL
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device pnp 2e.0a off end # PME
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end # f71869ad
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end #LPC
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device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
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device pci 14.5 off end # OHCI FS/LS USB
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device pci 14.5 on end # OHCI FS/LS USB (0x4399)
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device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
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device pci 15.0 off end # PCIe PortA
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device pci 15.0 on end # PCIe PortA (0x43a0) GbE MAC: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 (10ec:8168)
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device pci 15.1 off end # PCIe PortB
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device pci 15.2 off end # PCIe PortC
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device pci 15.3 off end # PCIe PortD
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device pci 16.0 off end # OHCI USB 10-13
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device pci 16.2 off end # EHCI USB 10-13
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device pci 16.0 on end # OHCI USB 10-13 (0x4397)
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device pci 16.2 on end # EHCI USB 10-13 (0x4396)
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register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
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register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
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#set up SB800 Fan control registers and IMC fan controls
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# Set up SB800 Fan control registers and IMC fan controls
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# TODO: verify SB handles the HW monitor and not the super io (PME)
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register "imc_port_address" = "0x6E" # 0x2E and 0x6E are common
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register "fan0_enabled" = "1"
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register "fan1_enabled" = "1"
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@ -150,6 +169,11 @@ chip northbridge/amd/agesa/family14/root_complex
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device pci 18.6 on end
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device pci 18.7 on end
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#
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# TODO: Verify the proper SocketId/MemChannelId/DimmId addresses of the SPD
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# with i2cdump tool.
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# Notes: 0xa0=0x50*2, 0xa2=0x51*2.. 0x50-0x54 are usually RAM modules on the SMBus.
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#
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register "spdAddrLookup" = "
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{
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{ {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
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@ -2,6 +2,7 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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* Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -211,6 +212,7 @@
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*/
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#define GEC_CONFIG 0
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/* FIXME: Verify this for sound to work! */
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static const CODECENTRY persimmon_codec_alc269[] =
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{
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/* NID, PinConfig */
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@ -228,6 +230,7 @@ static const CODECENTRY persimmon_codec_alc269[] =
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{0xff, 0xffffffff} /* end of table */
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};
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/* FIXME: Verify this for sound to work! */
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static const CODECTBLLIST codec_tablelist[] =
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{
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{0x010ec0269, (CODECENTRY*)&persimmon_codec_alc269[0]},
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@ -2,6 +2,7 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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* Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -31,7 +32,7 @@
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#include <cpu/x86/mtrr.h>
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#include "agesawrapper.h"
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#include "cpu/x86/bist.h"
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#include "superio/fintek/f81865f/f81865f_early_serial.c"
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#include "superio/fintek/f71869ad/f71869ad.h"
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#include "cpu/x86/lapic.h"
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#include "drivers/pc80/i8254.c"
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#include "drivers/pc80/i8259.c"
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@ -45,7 +46,8 @@
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void disable_cache_as_ram(void); /* cache_as_ram.inc */
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
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#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
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/* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */
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#define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1)
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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@ -70,7 +72,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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sb_Poweron_Init();
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post_code(0x31);
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f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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f71869ad_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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console_init();
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}
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