intel/amenia: Add GPE routing settings
This patch sets the devicetree for gpe0_dw configuration and also configures the GPIO lines for SCI. EC_SCI_GPI is configured to proper value. BUG = chrome-os-partner:53438 TEST = Toggle pch_sci_l from ec console using gpioset command and see that the sci counter increases in /sys/firmware/acpi/interrupt and also 9 in /proc/interrupt Change-Id: I3ae9ef7c6a3c8688bcb6cb4c73f5618e7cde342c Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15325 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -18,6 +18,15 @@ chip soc/intel/apollolake
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# LPSS S0ix Enable
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register "lpss_s0ix_enable" = "1"
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route, i.e., if this route changes then the affected GPE
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# offset bits also need to be changed. This sets the PMC register
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# GPE_CFG fields.
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register "gpe0_dw1" = "PMC_GPE_N_31_0"
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register "gpe0_dw2" = "PMC_GPE_N_63_32"
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register "gpe0_dw3" = "PMC_GPE_SW_31_0"
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device domain 0 on
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device pci 00.0 on end # - Host Bridge
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device pci 00.1 on end # - DPTF
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@ -20,9 +20,11 @@
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#include <ec/google/chromeec/ec_commands.h>
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/* This is the GPE status bit.
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TODO: Fix this to proper bit matching GPE routing table */
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#define EC_SCI_GPI 15
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/*
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* GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0
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* which is North community
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*/
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#define EC_SCI_GPI GPE0_DW1_11
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#define MAINBOARD_EC_SCI_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
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@ -239,7 +239,7 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1),
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PAD_CFG_GPI(GPIO_9, UP_20K, DEEP), /* SPI_TPM_IRQ_N */
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PAD_NC(GPIO_10, DN_20K), /* RSVD for MIPI (unused) */
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PAD_CFG_GPI_SCI(GPIO_11, UP_20K, DEEP, LEVEL, NONE),
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PAD_CFG_GPI_SCI(GPIO_11, UP_20K, DEEP, EDGE_SINGLE, INVERT),
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/* SOC_WAKE_SCI_N */
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PAD_NC(GPIO_12, DN_20K),
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PAD_NC(GPIO_13, DN_20K),
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