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intel/amenia: Add GPE routing settings 

This patch sets the devicetree for gpe0_dw configuration
and also configures the GPIO lines for SCI. EC_SCI_GPI
is configured to proper value.

BUG = chrome-os-partner:53438
TEST = Toggle pch_sci_l from ec console using gpioset command
       and see that the sci counter increases in /sys/firmware/acpi/interrupt
       and also 9 in /proc/interrupt

Change-Id: I3ae9ef7c6a3c8688bcb6cb4c73f5618e7cde342c
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15325
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Shaunak Saha 2016-06-10 19:36:49 -07:00 committed by Aaron Durbin
parent 7f149c7bb4
commit 6e5c5a15bc
3 changed files with 15 additions and 4 deletions
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9
src/mainboard/intel/amenia/devicetree.cb
View File

@ -18,6 +18,15 @@ chip soc/intel/apollolake
# LPSS S0ix Enable
register "lpss_s0ix_enable" = "1"
# GPE configuration
# Note that GPE events called out in ASL code rely on this
# route, i.e., if this route changes then the affected GPE
# offset bits also need to be changed. This sets the PMC register
# GPE_CFG fields.
register "gpe0_dw1" = "PMC_GPE_N_31_0"
register "gpe0_dw2" = "PMC_GPE_N_63_32"
register "gpe0_dw3" = "PMC_GPE_SW_31_0"
device domain 0 on
device pci 00.0 on end # - Host Bridge
device pci 00.1 on end # - DPTF

8
src/mainboard/intel/amenia/ec.h
View File

@ -20,9 +20,11 @@
#include <ec/google/chromeec/ec_commands.h>
/* This is the GPE status bit.
TODO: Fix this to proper bit matching GPE routing table */
#define EC_SCI_GPI 15
/*
* GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0
* which is North community
*/
#define EC_SCI_GPI GPE0_DW1_11
#define MAINBOARD_EC_SCI_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\

2
src/mainboard/intel/amenia/gpio.h
View File

@ -239,7 +239,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1),
PAD_CFG_GPI(GPIO_9, UP_20K, DEEP), /* SPI_TPM_IRQ_N */
PAD_NC(GPIO_10, DN_20K), /* RSVD for MIPI (unused) */
PAD_CFG_GPI_SCI(GPIO_11, UP_20K, DEEP, LEVEL, NONE),
PAD_CFG_GPI_SCI(GPIO_11, UP_20K, DEEP, EDGE_SINGLE, INVERT),
/* SOC_WAKE_SCI_N */
PAD_NC(GPIO_12, DN_20K),
PAD_NC(GPIO_13, DN_20K),