From 6e61c5ec00ebfac6c7e695e9eedd53a421e75894 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 4 Mar 2020 18:32:37 +0100 Subject: [PATCH] soc/intel/braswell: Generate microcode binaries from tree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Automatically add microcode binaries from intel-microcode 3rdparty respository for Braswell processors using Makefile. Signed-off-by: Michał Żygowski Change-Id: Iec57e4d5cd63b9bccc869bf178053f1c99b81b9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/39320 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Angel Pons Reviewed-by: Matt DeVillier --- src/soc/intel/braswell/Kconfig | 1 - src/soc/intel/braswell/Makefile.inc | 2 ++ 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 5b6a9237e7..a437db2580 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -15,7 +15,6 @@ config CPU_SPECIFIC_OPTIONS select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select SUPPORT_CPU_UCODE_IN_CBFS - select MICROCODE_BLOB_NOT_IN_BLOB_REPO select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select HAVE_SMI_HANDLER select NO_FIXED_XIP_ROM_SIZE diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index d2626e865e..5923e39a30 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -68,6 +68,8 @@ CPPFLAGS_common += -I$(call strip_quotes,$(CONFIG_FSP_HEADER_PATH)) CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARDDIR) +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-4c-*) + ifneq ($(CONFIG_VGA_BIOS_FILE),) #we will assume that the vbios names will remain as they are now: vgabios.bin and vgabios_c0.bin BRASWELL_C0_VBIOS= $(subst .bin,_c0.bin,$(call strip_quotes,$(CONFIG_VGA_BIOS_FILE)))