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soc/intel/alderlake: Hook up UPD EnableHwpScalabilityTracking 

Hook the newly exposed EnableHwpScalabilityTracking UPD up so that
boards can configure is via devicetree.

BUG=b:280021171
TEST=Verified by enabling/disabling the UPD on google/brya

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I4c8845c445d46caa30a0245386ab9cd690d2623f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74722
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This commit is contained in:
Bora Guvendik 2023-04-24 18:12:19 -07:00 committed by Nick Vaccaro
parent 7d1a037f88
commit 6e64c01d08
2 changed files with 11 additions and 0 deletions
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7
src/soc/intel/alderlake/chip.h
View File

@ -744,6 +744,13 @@ struct soc_intel_alderlake_config {
* Set this to 1 in order to disable SaGV reordering. * Set this to 1 in order to disable SaGV reordering.
*/ */
bool disable_sagv_reorder; bool disable_sagv_reorder;
/*
* Enable or Disable hwp scalability tracking.
* Default is set to 1.
* Set this to 0 in order to disable hwp scalability tracking.
*/
bool enable_hwp_scalability_tracking;
}; };
typedef struct soc_intel_alderlake_config config_t; typedef struct soc_intel_alderlake_config config_t;

4
src/soc/intel/alderlake/fsp_params.c
View File

@ -1024,6 +1024,10 @@ static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg,
s_cfg->C1e = 0; s_cfg->C1e = 0;
else else
s_cfg->C1e = 1; s_cfg->C1e = 1;
#if CONFIG(SOC_INTEL_RAPTORLAKE)
s_cfg->EnableHwpScalabilityTracking = config->enable_hwp_scalability_tracking;
#endif
} }
static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg, static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg,