soc/intel/common,skl: set MSR LT_LOCK_MEMORY once, not per thread

The MSR LT_LOCK_MEMORY is package-scoped, not thread-scoped. Only set it
once.

Tested on Acer ES1-572 by checking chipsec results.

Change-Id: If3d61fcbc9ab99b6c1b7b74881e6d9c6be04a498
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

src/soc/intel/common/block/cpu/cpulib.c

@@ -355,7 +355,7 @@ void mca_configure(void)
 	}
 }
 
-void cpu_lt_lock_memory(void *unused)
+void cpu_lt_lock_memory(void)
 {
 	msr_set(MSR_LT_CONTROL, LT_CONTROL_LOCK);
 }

src/soc/intel/common/block/include/intelblocks/cpulib.h

@@ -151,7 +151,7 @@ uint32_t cpu_get_max_turbo_ratio(void);
 void mca_configure(void);
 
 /* Lock chipset memory registers to protect SMM */
-void cpu_lt_lock_memory(void *unused);
+void cpu_lt_lock_memory(void);
 
 /* Get a supported PRMRR size in bytes with respect to users choice */
 int get_valid_prmrr_size(void);

src/soc/intel/common/block/sgx/sgx.c

@@ -205,9 +205,9 @@ void sgx_configure(void *unused)
 	if (owner_epoch_update() < 0)
 		return;
 
+	/* Ensure to lock memory before reloading microcode patch */
 	if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY))
-		/* Ensure to lock memory before reload microcode patch */
-		cpu_lt_lock_memory(NULL);
+		cpu_lt_lock_memory();
 
 	/*
 	 * Update just on the first CPU in the core. Other siblings

src/soc/intel/skylake/finalize.c

@@ -84,8 +84,7 @@ static void soc_lockdown(struct device *dev)
 		pci_write_config8(dev, GEN_PMCON_A, reg8);
 	}
 
-	/* Lock chipset memory registers to protect SMM */
-	mp_run_on_all_cpus(cpu_lt_lock_memory, NULL);
+	cpu_lt_lock_memory();
 }
 
 static void soc_finalize(void *unused)