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intel: Turn `DEFAULT_RCBA` into a Kconfig symbol 

Create `FIXED_RCBA_MMIO_BASE` and use it everywhere, except in cases
where a pointer cast would be necessary. Instances in Sandy Bridge MRC
code were left as-is intentionally, so as not to collide with another
cleanup patch train.

Tested with BUILD_TIMELESS=1, these boards remain identical:
- Asus P8Z77-V LX2
- Packard Bell MS2290

Change-Id: I642958fbd6f02dbf54812d6a75d6bc3087acc77a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50036
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2021-01-28 13:56:18 +01:00 committed by Patrick Georgi
parent 6e0ca68c82
commit 6e732d34a0
29 changed files with 33 additions and 44 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/emulation/qemu-q35/bootblock.c
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@ -36,7 +36,7 @@ static void bootblock_southbridge_init(void)
/* Enable RCBA */ /* Enable RCBA */
pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA,
(uintptr_t)DEFAULT_RCBA | 1); CONFIG_FIXED_RCBA_MMIO_BASE | 1);
} }
void bootblock_soc_init(void) void bootblock_soc_init(void)

3
src/northbridge/intel/gm45/acpi/gm45.asl
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@ -3,7 +3,6 @@
#include "hostbridge.asl" #include "hostbridge.asl"
#include "../memmap.h" #include "../memmap.h"
#include <southbridge/intel/i82801ix/i82801ix.h> #include <southbridge/intel/i82801ix/i82801ix.h>
#include <southbridge/intel/common/rcba.h>
/* PCI Device Resource Consumption */ /* PCI Device Resource Consumption */
Device (PDRC) Device (PDRC)
@ -14,7 +13,7 @@ Device (PDRC)
// This does not seem to work correctly yet - set values statically for // This does not seem to work correctly yet - set values statically for
// now. // now.
Name (PDRS, ResourceTemplate() { Name (PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, 0x00004000)
Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)

2
src/northbridge/intel/gm45/pcie.c
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@ -264,7 +264,7 @@ static void setup_rcrb(const int peg_enabled)
/* Link1: target port 0, component id 2 (ICH), link valid. */ /* Link1: target port 0, component id 2 (ICH), link valid. */
DMIBAR32(DMILE1D) = (0 << 24) | (2 << 16) | (1 << 0); DMIBAR32(DMILE1D) = (0 << 24) | (2 << 16) | (1 << 0);
DMIBAR32(DMILE1A) = (uintptr_t)DEFAULT_RCBA; DMIBAR32(DMILE1A) = CONFIG_FIXED_RCBA_MMIO_BASE;
/* Link2: component ID 1 (MCH), link valid */ /* Link2: component ID 1 (MCH), link valid */
DMIBAR32(DMILE2D) = DMIBAR32(DMILE2D) =

3
src/northbridge/intel/haswell/acpi/hostbridge.asl
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@ -1,7 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include "../haswell.h" #include "../haswell.h"
#include <southbridge/intel/common/rcba.h>
Name (_HID, EISAID ("PNP0A08")) // PCIe Name (_HID, EISAID ("PNP0A08")) // PCIe
Name (_CID, EISAID ("PNP0A03")) // PCI Name (_CID, EISAID ("PNP0A03")) // PCI
@ -175,7 +174,7 @@ Device (PDRC)
Name (_UID, 1) Name (_UID, 1)
Name (PDRS, ResourceTemplate () { Name (PDRS, ResourceTemplate () {
Memory32Fixed (ReadWrite, DEFAULT_RCBA, 0x00004000) Memory32Fixed (ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, 0x00004000)
Memory32Fixed (ReadWrite, DEFAULT_MCHBAR, 0x00008000) Memory32Fixed (ReadWrite, DEFAULT_MCHBAR, 0x00008000)
Memory32Fixed (ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed (ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed (ReadWrite, DEFAULT_EPBAR, 0x00001000) Memory32Fixed (ReadWrite, DEFAULT_EPBAR, 0x00001000)

2
src/northbridge/intel/haswell/northbridge.c
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@ -511,7 +511,7 @@ static void northbridge_topology_init(void)
reg32 &= ~(0xffff << 16); reg32 &= ~(0xffff << 16);
reg32 |= 1 | (2 << 16); reg32 |= 1 | (2 << 16);
DMIBAR32(DMILE1D) = reg32; DMIBAR32(DMILE1D) = reg32;
DMIBAR64(DMILE1A) = (uintptr_t)DEFAULT_RCBA; DMIBAR64(DMILE1A) = CONFIG_FIXED_RCBA_MMIO_BASE;
DMIBAR64(DMILE2A) = (uintptr_t)DEFAULT_EPBAR; DMIBAR64(DMILE2A) = (uintptr_t)DEFAULT_EPBAR;
reg32 = DMIBAR32(DMILE2D); reg32 = DMIBAR32(DMILE2D);

2
src/northbridge/intel/haswell/romstage.c
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@ -56,7 +56,7 @@ void mainboard_romstage_entry(void)
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.hpet_address = HPET_ADDR, .hpet_address = HPET_ADDR,
.rcba = (uintptr_t)DEFAULT_RCBA, .rcba = CONFIG_FIXED_RCBA_MMIO_BASE,
.pmbase = DEFAULT_PMBASE, .pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE, .gpiobase = DEFAULT_GPIOBASE,
.temp_mmio_base = 0xfed08000, .temp_mmio_base = 0xfed08000,

3
src/northbridge/intel/i945/acpi/i945.asl
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@ -2,7 +2,6 @@
#include "hostbridge.asl" #include "hostbridge.asl"
#include "../i945.h" #include "../i945.h"
#include <southbridge/intel/common/rcba.h>
/* Operating System Capabilities Method */ /* Operating System Capabilities Method */
Method (_OSC, 4) Method (_OSC, 4)
@ -38,7 +37,7 @@ Device (PDRC)
//}) //})
Name (PDRS, ResourceTemplate() { Name (PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, 0x00004000)
Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)

2
src/northbridge/intel/i945/early_init.c
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@ -730,7 +730,7 @@ static void i945_setup_root_complex_topology(void)
reg32 |= (1 << 0); reg32 |= (1 << 0);
DMIBAR32(DMILE1D) = reg32; DMIBAR32(DMILE1D) = reg32;
DMIBAR32(DMILE1A) = (uintptr_t)DEFAULT_RCBA; DMIBAR32(DMILE1A) = CONFIG_FIXED_RCBA_MMIO_BASE;
DMIBAR32(DMILE2D) |= (1 << 16) | (1 << 0); DMIBAR32(DMILE2D) |= (1 << 16) | (1 << 0);

3
src/northbridge/intel/ironlake/acpi/ironlake.asl
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@ -2,7 +2,6 @@
#include "../ironlake.h" #include "../ironlake.h"
#include "hostbridge.asl" #include "hostbridge.asl"
#include <southbridge/intel/common/rcba.h>
/* PCI Device Resource Consumption */ /* PCI Device Resource Consumption */
Device (PDRC) Device (PDRC)
@ -11,7 +10,7 @@ Device (PDRC)
Name (_UID, 1) Name (_UID, 1)
Name (PDRS, ResourceTemplate() { Name (PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, 0x00004000)
Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000)
Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)

3
src/northbridge/intel/pineview/acpi/pineview.asl
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@ -2,7 +2,6 @@
#include "hostbridge.asl" #include "hostbridge.asl"
#include "../memmap.h" #include "../memmap.h"
#include <southbridge/intel/common/rcba.h>
/* PCI Device Resource Consumption */ /* PCI Device Resource Consumption */
Device (PDRC) Device (PDRC)
@ -13,7 +12,7 @@ Device (PDRC)
/* This does not seem to work correctly yet - set values statically for now. */ /* This does not seem to work correctly yet - set values statically for now. */
Name (PDRS, ResourceTemplate() { Name (PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, 0x00004000)
Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)

3
src/northbridge/intel/sandybridge/acpi/sandybridge.asl
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@ -2,7 +2,6 @@
#include "hostbridge.asl" #include "hostbridge.asl"
#include "peg.asl" #include "peg.asl"
#include <southbridge/intel/common/rcba.h>
/* PCI Device Resource Consumption */ /* PCI Device Resource Consumption */
Device (PDRC) Device (PDRC)
@ -11,7 +10,7 @@ Device (PDRC)
Name (_UID, 1) Name (_UID, 1)
Name (PDRS, ResourceTemplate() { Name (PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, 0x00004000)
// Filled by _CRS // Filled by _CRS
Memory32Fixed(ReadWrite, 0, 0x00008000, MCHB) Memory32Fixed(ReadWrite, 0, 0x00008000, MCHB)
Memory32Fixed(ReadWrite, 0, 0x00001000, DMIB) Memory32Fixed(ReadWrite, 0, 0x00001000, DMIB)

3
src/northbridge/intel/x4x/acpi/x4x.asl
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@ -2,7 +2,6 @@
#include "hostbridge.asl" #include "hostbridge.asl"
#include "../memmap.h" #include "../memmap.h"
#include <southbridge/intel/common/rcba.h>
/* PCI Device Resource Consumption */ /* PCI Device Resource Consumption */
Device (PDRC) Device (PDRC)
@ -11,7 +10,7 @@ Device (PDRC)
Name (_UID, 1) Name (_UID, 1)
Name (PDRS, ResourceTemplate() { Name (PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, 0x00004000)
Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)

2
src/southbridge/intel/bd82x6x/acpi/pch.asl
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@ -181,7 +181,7 @@ Scope(\)
// ICH7 Root Complex Register Block. Memory Mapped through RCBA) // ICH7 Root Complex Register Block. Memory Mapped through RCBA)
OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, 0x4000)
Field(RCRB, DWordAcc, Lock, Preserve) Field(RCRB, DWordAcc, Lock, Preserve)
{ {
Offset(0x0000), // Backbone Offset(0x0000), // Backbone

2
src/southbridge/intel/bd82x6x/early_pch.c
View File

@ -218,7 +218,7 @@ void early_pch_init_native(void)
static void pch_enable_bars(void) static void pch_enable_bars(void)
{ {
pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); pci_write_config32(PCH_LPC_DEV, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1);
pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1);

2
src/southbridge/intel/bd82x6x/smihandler.c
View File

@ -186,7 +186,7 @@ void southbridge_smm_xhci_sleep(u8 slp_type)
return; return;
/* Verify that RCBA is still valid */ /* Verify that RCBA is still valid */
if (pci_read_config32(PCH_LPC_DEV, RCBA) != ((u32)DEFAULT_RCBA | RCBA_ENABLE)) if (pci_read_config32(PCH_LPC_DEV, RCBA) != (CONFIG_FIXED_RCBA_MMIO_BASE | RCBA_ENABLE))
return; return;
if (RCBA32(FD) & PCH_DISABLE_XHCI) if (RCBA32(FD) & PCH_DISABLE_XHCI)

4
src/southbridge/intel/common/Kconfig
View File

@ -104,6 +104,10 @@ config SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
bool bool
depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE
config FIXED_RCBA_MMIO_BASE
hex
default 0xfed1c000
config FIXED_SMBUS_IO_BASE config FIXED_SMBUS_IO_BASE
hex hex
depends on SOUTHBRIDGE_INTEL_COMMON_SMBUS depends on SOUTHBRIDGE_INTEL_COMMON_SMBUS

10
src/southbridge/intel/common/rcba.h
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@ -3,9 +3,7 @@
#ifndef SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H #ifndef SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H
#define SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H #define SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H
#ifndef __ACPI__ #define DEFAULT_RCBA ((u8 *)CONFIG_FIXED_RCBA_MMIO_BASE)
#define DEFAULT_RCBA ((u8 *)0xfed1c000)
/* Root Complex Register Block */ /* Root Complex Register Block */
#define RCBA 0xf0 #define RCBA 0xf0
@ -23,10 +21,4 @@
#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) #define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)
#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or) #define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)
#else
#define DEFAULT_RCBA 0xfed1c000
#endif /* __ACPI__ */
#endif /* SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H */ #endif /* SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H */

2
src/southbridge/intel/i82801gx/acpi/ich7.asl
View File

@ -110,7 +110,7 @@ Scope(\)
// ICH7 Root Complex Register Block. Memory Mapped through RCBA) // ICH7 Root Complex Register Block. Memory Mapped through RCBA)
OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, 0x4000)
Field(RCRB, DWordAcc, Lock, Preserve) Field(RCRB, DWordAcc, Lock, Preserve)
{ {
// Backbone // Backbone

2
src/southbridge/intel/i82801gx/early_init.c
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@ -48,7 +48,7 @@ void i82801gx_lpc_setup(void)
void i82801gx_setup_bars(void) void i82801gx_setup_bars(void)
{ {
const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
pci_write_config32(d31f0, RCBA, (uint32_t)DEFAULT_RCBA | 1); pci_write_config32(d31f0, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1);
pci_write_config32(d31f0, PMBASE, DEFAULT_PMBASE | 1); pci_write_config32(d31f0, PMBASE, DEFAULT_PMBASE | 1);
pci_write_config8(d31f0, ACPI_CNTL, ACPI_EN); pci_write_config8(d31f0, ACPI_CNTL, ACPI_EN);

2
src/southbridge/intel/i82801ix/acpi/ich9.asl
View File

@ -110,7 +110,7 @@ Scope(\)
// ICH9 Root Complex Register Block. Memory Mapped through RCBA) // ICH9 Root Complex Register Block. Memory Mapped through RCBA)
OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, 0x4000)
Field(RCRB, DWordAcc, Lock, Preserve) Field(RCRB, DWordAcc, Lock, Preserve)
{ {
Offset(0x0000), // Backbone Offset(0x0000), // Backbone

2
src/southbridge/intel/i82801ix/early_init.c
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@ -51,7 +51,7 @@ void i82801ix_early_init(void)
enable_smbus(); enable_smbus();
/* Set up RCBA. */ /* Set up RCBA. */
pci_write_config32(d31f0, RCBA, (uintptr_t)DEFAULT_RCBA | 1); pci_write_config32(d31f0, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1);
/* Set up PMBASE. */ /* Set up PMBASE. */
pci_write_config32(d31f0, D31F0_PMBASE, DEFAULT_PMBASE | 1); pci_write_config32(d31f0, D31F0_PMBASE, DEFAULT_PMBASE | 1);

2
src/southbridge/intel/i82801jx/acpi/ich10.asl
View File

@ -112,7 +112,7 @@ Scope(\)
// ICH10 Root Complex Register Block. Memory Mapped through RCBA) // ICH10 Root Complex Register Block. Memory Mapped through RCBA)
OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, 0x4000)
Field(RCRB, DWordAcc, Lock, Preserve) Field(RCRB, DWordAcc, Lock, Preserve)
{ {
Offset(0x0000), // Backbone Offset(0x0000), // Backbone

2
src/southbridge/intel/i82801jx/early_init.c
View File

@ -50,7 +50,7 @@ void i82801jx_setup_bars(void)
const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
/* Set up RCBA. */ /* Set up RCBA. */
pci_write_config32(d31f0, RCBA, (uintptr_t)DEFAULT_RCBA | 1); pci_write_config32(d31f0, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1);
/* Set up PMBASE. */ /* Set up PMBASE. */
pci_write_config32(d31f0, D31F0_PMBASE, DEFAULT_PMBASE | 1); pci_write_config32(d31f0, D31F0_PMBASE, DEFAULT_PMBASE | 1);

2
src/southbridge/intel/ibexpeak/bootblock.c
View File

@ -80,7 +80,7 @@ void bootblock_early_southbridge_init(void)
/* Enable RCBA */ /* Enable RCBA */
pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0); pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0);
pci_write_config32(lpc_dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); pci_write_config32(lpc_dev, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1);
enable_port80_on_lpc(); enable_port80_on_lpc();
set_spi_speed(); set_spi_speed();

2
src/southbridge/intel/ibexpeak/early_pch.c
View File

@ -30,7 +30,7 @@ static void pch_default_disable(void)
void ibexpeak_setup_bars(void) void ibexpeak_setup_bars(void)
{ {
printk(BIOS_DEBUG, "Setting up static southbridge registers..."); printk(BIOS_DEBUG, "Setting up static southbridge registers...");
pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1);
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
/* Enable ACPI BAR */ /* Enable ACPI BAR */

2
src/southbridge/intel/lynxpoint/acpi/pch.asl
View File

@ -19,7 +19,7 @@ Scope (\)
} }
// Root Complex Register Block // Root Complex Register Block
OperationRegion (RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) OperationRegion (RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, 0x4000)
Field (RCRB, DWordAcc, Lock, Preserve) Field (RCRB, DWordAcc, Lock, Preserve)
{ {
Offset (0x3404), // High Performance Timer Configuration Offset (0x3404), // High Performance Timer Configuration

2
src/southbridge/intel/lynxpoint/bootblock.c
View File

@ -7,7 +7,7 @@
static void map_rcba(void) static void map_rcba(void)
{ {
pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); pci_write_config32(PCH_LPC_DEV, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1);
} }
static void enable_port80_on_lpc(void) static void enable_port80_on_lpc(void)

2
src/southbridge/intel/lynxpoint/early_pch.c
View File

@ -36,7 +36,7 @@ enum pch_platform_type get_pch_platform_type(void)
static void pch_enable_bars(void) static void pch_enable_bars(void)
{ {
pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); pci_write_config32(PCH_LPC_DEV, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1);
pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1);
/* Enable ACPI BAR */ /* Enable ACPI BAR */

4
src/southbridge/intel/lynxpoint/lpc.c
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@ -557,9 +557,9 @@ static void pch_lpc_add_mmio_resources(struct device *dev)
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
/* RCBA */ /* RCBA */
if ((uintptr_t)DEFAULT_RCBA < default_decode_base) { if (CONFIG_FIXED_RCBA_MMIO_BASE < default_decode_base) {
res = new_resource(dev, RCBA); res = new_resource(dev, RCBA);
res->base = (resource_t)(uintptr_t)DEFAULT_RCBA; res->base = (resource_t)CONFIG_FIXED_RCBA_MMIO_BASE;
res->size = 16 * 1024; res->size = 16 * 1024;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED | IORESOURCE_RESERVE; IORESOURCE_FIXED | IORESOURCE_RESERVE;