From 6e7e8bffba576c907b238ab6aaa47d13b1737e58 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Fri, 2 Dec 2022 02:21:11 +0530
Subject: [PATCH] =?UTF-8?q?mb/google/rex:=20Add=20MPTS=20method=C2=A0for?=
 =?UTF-8?q?=20WWAN=20over=20PCIe?=
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This patch generates the following for the mainboard:

Scope (\_SB)
{
        Method (MPTS, 1, Serialized)
        {
            Local0 = \_SB.PCI0.RP06.RTD3._STA ()
            If ((Local0 == One))
            {
                \_SB.PCI0.RP06.PXSX.DPTS (Arg0)
            }
        }
}

Change-Id: I27ade63cfe0586aee9f03ba816b2590f14dcb610
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70229
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/rex/mainboard.c          | 34 ++++++++++++++++++-
 .../google/rex/variants/rex0/overridetree.cb  |  8 +++--
 2 files changed, 39 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/rex/mainboard.c b/src/mainboard/google/rex/mainboard.c
index 2414eddc77..a076ec210d 100644
--- a/src/mainboard/google/rex/mainboard.c
+++ b/src/mainboard/google/rex/mainboard.c
@@ -1,12 +1,16 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <acpi/acpi.h>
+#include <acpi/acpigen.h>
 #include <baseboard/variants.h>
 #include <device/device.h>
+#include <drivers/wwan/fm/chip.h>
 #include <ec/ec.h>
 #include <fw_config.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
+WEAK_DEV_PTR(rp6_wwan);
+
 static void mainboard_init(void *chip_info)
 {
 	const struct pad_config *pads;
@@ -15,9 +19,37 @@ static void mainboard_init(void *chip_info)
 	gpio_configure_pads(pads, num);
 }
 
+static void mainboard_generate_wwan_shutdown(const struct device *dev)
+{
+	const struct drivers_wwan_fm_config *config = config_of(dev);
+	const struct device *parent = dev->bus->dev;
+
+	if (!config)
+		return;
+	if (config->rtd3dev) {
+		acpigen_write_store();
+		acpigen_emit_namestring(acpi_device_path_join(parent, "RTD3._STA"));
+		acpigen_emit_byte(LOCAL0_OP);
+		acpigen_write_if_lequal_op_int(LOCAL0_OP, ONE_OP);
+		{
+			acpigen_emit_namestring(acpi_device_path_join(dev, "DPTS"));
+			acpigen_emit_byte(ARG0_OP);
+		}
+		acpigen_write_if_end();
+	}
+}
+
 static void mainboard_fill_ssdt(const struct device *dev)
 {
-	/* TODO: Add mainboard-specific SSDT entries */
+	const struct device *wwan = DEV_PTR(rp6_wwan);
+
+	if (wwan) {
+		acpigen_write_scope("\\_SB");
+		acpigen_write_method_serialized("MPTS", 1);
+		mainboard_generate_wwan_shutdown(wwan);
+		acpigen_write_method_end(); /* Method */
+		acpigen_write_scope_end(); /* Scope */
+	}
 }
 
 static void add_fw_config_oem_string(const struct fw_config *config, void *arg)
diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb
index 6ec0bf2cad..57e872854e 100644
--- a/src/mainboard/google/rex/variants/rex0/overridetree.cb
+++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb
@@ -450,7 +450,9 @@ chip soc/intel/meteorlake
 				register "srcclk_pin" = "3"
 				register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
 				register "skip_on_off_support" = "true"
-				device generic 0 alias rp6_rtd3 on end
+				device generic 0 alias rp6_rtd3 on
+					probe CELLULAR CELLULAR_PCIE
+				end
 			end
 			chip drivers/wwan/fm
 				register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E07)"
@@ -459,7 +461,9 @@ chip soc/intel/meteorlake
 				register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F10)"
 				register "add_acpi_dma_property" = "true"
 				use rp6_rtd3 as rtd3dev
-				device generic 0 on end
+				device generic 0 alias rp6_wwan on
+					probe CELLULAR CELLULAR_PCIE
+				end
 			end
 		end	#PCIE6 WWAN card
 		device ref pcie_rp7 on