GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/*/chip: Remove unused devicetree entry 

InternalGfx isn't used so drop it.

Change-Id: I12f424d8d883e065ef8d007e56a8bff41a7fae53
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Patrick Rudolph 2020-11-03 19:23:34 +01:00 committed by Patrick Georgi
parent 2f6875518e
commit 6e98292821
10 changed files with 1 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/google/drallion/variants/drallion/devicetree.cb
View File

@ -30,7 +30,6 @@ chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "SaGv_Enabled"
register "InternalGfx" = "1"
register "SkipExtGfxScan" = "1"
register "PchPmSlpS3MinAssert" = "3" # 50ms
register "PchPmSlpS4MinAssert" = "4" # 4s

1
src/mainboard/google/hatch/variants/baseboard/devicetree.cb
View File

@ -18,7 +18,6 @@ chip soc/intel/cannonlake
register "gen3_dec" = "0x00fc0901"
# FSP configuration
register "InternalGfx" = "1"
register "SkipExtGfxScan" = "1"
register "SataSalpSupport" = "1"
register "SataMode" = "Sata_AHCI"

1
src/mainboard/google/sarien/variants/arcada/devicetree.cb
View File

@ -19,7 +19,6 @@ chip soc/intel/cannonlake
register "SataMode" = "Sata_AHCI"
register "SataPortsEnable[2]" = "1"
register "SataPortsDevSlp[2]" = "1"
register "InternalGfx" = "1"
register "SkipExtGfxScan" = "1"
register "PchPmSlpS3MinAssert" = "3" # 50ms
register "PchPmSlpS4MinAssert" = "4" # 4s

1
src/mainboard/google/sarien/variants/sarien/devicetree.cb
View File

@ -23,7 +23,6 @@ chip soc/intel/cannonlake
register "SataPortsDevSlp[0]" = "1"
register "SataPortsDevSlp[1]" = "1"
register "SataPortsDevSlp[2]" = "1"
register "InternalGfx" = "1"
register "SkipExtGfxScan" = "1"
register "PchPmSlpS3MinAssert" = "3" # 50ms
register "PchPmSlpS4MinAssert" = "4" # 4s

4
src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb
View File

@ -161,9 +161,7 @@ chip soc/intel/cannonlake
device domain 0 on
device pci 02.0 on # Integrated Graphics Device
register "InternalGfx" = "1"
end
device pci 02.0 on end # Integrated Graphics Device
device pci 14.3 on
chip drivers/wifi/generic
register "wake" = "PME_B0_EN_BIT"

1
src/soc/intel/cannonlake/chip.h
View File

@ -230,7 +230,6 @@ struct soc_intel_cannonlake_config {
/* Gfx related */
uint8_t IgdDvmt50PreAlloc;
uint8_t InternalGfx;
uint8_t SkipExtGfxScan;
uint32_t GraphicsConfigPtr;

1
src/soc/intel/elkhartlake/chip.h
View File

@ -140,7 +140,6 @@ struct soc_intel_elkhartlake_config {
/* Gfx related */
uint8_t IgdDvmt50PreAlloc;
uint8_t InternalGfx;
uint8_t SkipExtGfxScan;
uint32_t GraphicsConfigPtr;

1
src/soc/intel/icelake/chip.h
View File

@ -152,7 +152,6 @@ struct soc_intel_icelake_config {
/* Gfx related */
uint8_t IgdDvmt50PreAlloc;
uint8_t InternalGfx;
uint8_t SkipExtGfxScan;
uint32_t GraphicsConfigPtr;

1
src/soc/intel/jasperlake/chip.h
View File

@ -141,7 +141,6 @@ struct soc_intel_jasperlake_config {
/* Gfx related */
uint8_t IgdDvmt50PreAlloc;
uint8_t InternalGfx;
uint8_t SkipExtGfxScan;
uint32_t GraphicsConfigPtr;

1
src/soc/intel/tigerlake/chip.h
View File

@ -261,7 +261,6 @@ struct soc_intel_tigerlake_config {
/* Gfx related */
uint8_t IgdDvmt50PreAlloc;
uint8_t InternalGfx;
uint8_t SkipExtGfxScan;
uint32_t GraphicsConfigPtr;