i855: Remove useless memctrl indirection.
This needlessly complicates the code and increases register pressure on romcc chipsets. We did the same conversion on i440BX, i830, and others. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6112 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
parent
abc0c85516
commit
6e9ab97106
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@ -5,6 +5,7 @@
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#include <arch/romcc_io.h>
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#include <arch/hlt.h>
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#include <stdlib.h>
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#include <lib.h>
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#include "pc80/udelay_io.c"
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#include <pc80/mc146818rtc.h>
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#include <console/console.h>
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@ -26,17 +27,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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#include "northbridge/intel/i855/raminit.c"
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#include "northbridge/intel/i855/reset_test.c"
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#include "lib/generic_sdram.c"
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void main(unsigned long bist)
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{
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static const struct mem_controller memctrl[] = {
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{
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.d0 = PCI_DEV(0, 0, 1),
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.channel0 = { DIMM0, 0 },
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},
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};
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if (bist == 0) {
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#if 0
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enable_lapic();
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@ -58,10 +51,12 @@ void main(unsigned long bist)
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if (!bios_reset_detected()) {
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enable_smbus();
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#if 0
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dump_spd_registers(&memctrl[0]);
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dump_spd_registers();
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dump_smbus_registers();
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#endif
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sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
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sdram_set_registers();
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sdram_set_spd_registers();
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sdram_enable();
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}
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#if 0
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@ -27,6 +27,7 @@
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#include <arch/romcc_io.h>
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#include <arch/hlt.h>
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#include <stdlib.h>
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#include <lib.h>
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#include <spd.h>
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#include "pc80/udelay_io.c"
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#include <pc80/mc146818rtc.h>
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@ -48,17 +49,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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#include "northbridge/intel/i855/raminit.c"
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#include "northbridge/intel/i855/reset_test.c"
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#include "lib/generic_sdram.c"
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void main(unsigned long bist)
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{
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static const struct mem_controller memctrl[] = {
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{
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.d0 = PCI_DEV(0, 0, 1),
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.channel0 = { DIMM0, 0 },
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},
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};
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if (bist == 0) {
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#if 0
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enable_lapic();
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@ -80,10 +73,12 @@ void main(unsigned long bist)
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if (!bios_reset_detected()) {
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enable_smbus();
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#if 1
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dump_spd_registers(&memctrl[0]);
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dump_spd_registers();
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dump_smbus_registers();
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#endif
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sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
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sdram_set_registers();
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sdram_set_spd_registers();
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sdram_enable();
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}
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#if 0
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@ -18,6 +18,8 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <spd.h>
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static void print_debug_pci_dev(unsigned dev)
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{
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print_debug("PCI: ");
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@ -84,13 +86,13 @@ static inline void dump_pci_devices(void)
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}
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}
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static inline void dump_spd_registers(const struct mem_controller *ctrl)
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static inline void dump_spd_registers(void)
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{
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int i;
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print_debug("\n");
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for(i = 0; i < 2; i++) {
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unsigned device;
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device = ctrl->channel0[i];
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device = DIMM0 + i;
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if (device) {
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int j;
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print_debug("dimm: ");
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@ -127,7 +127,7 @@ static void die_on_spd_error(int spd_return_value)
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* @param dimm_socket_address SMBus address of DIMM socket to interrogate.
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* @return log2(page size) for each side of the DIMM.
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*/
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static struct dimm_size sdram_spd_get_page_size(uint16_t dimm_socket_address)
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static struct dimm_size sdram_spd_get_page_size(u8 dimm_socket_address)
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{
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uint16_t module_data_width;
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int value;
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@ -187,7 +187,7 @@ static struct dimm_size sdram_spd_get_page_size(uint16_t dimm_socket_address)
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* @param dimm_socket_address SMBus address of DIMM socket to interrogate.
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* @return Width in bits of each DIMM side's DRAMs.
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*/
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static struct dimm_size sdram_spd_get_width(uint16_t dimm_socket_address)
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static struct dimm_size sdram_spd_get_width(u8 dimm_socket_address)
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{
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int value;
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struct dimm_size width;
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@ -274,17 +274,15 @@ static struct dimm_size spd_get_dimm_size(unsigned dimm)
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/**
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* Scan for compatible DIMMs.
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*
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* @param ctrl PCI addresses of memory controller functions, and SMBus
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* addresses of DIMM slots on the mainboard.
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* @return A bitmask indicating which sockets contain a compatible DIMM.
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*/
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static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
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static uint8_t spd_get_supported_dimms(void)
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{
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int i;
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uint8_t dimm_mask = 0;
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for (i = 0; i < DIMM_SOCKETS; i++) {
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uint16_t dimm = ctrl->channel0[i];
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u8 dimm = DIMM0 + i;
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#ifdef VALIDATE_DIMM_COMPATIBILITY
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struct dimm_size page_size;
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@ -404,7 +402,7 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
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}
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}
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static void set_initialize_complete(const struct mem_controller *ctrl)
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static void set_initialize_complete(void)
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{
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uint32_t drc_reg;
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@ -413,7 +411,7 @@ static void set_initialize_complete(const struct mem_controller *ctrl)
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pci_write_config32(NORTHBRIDGE_MMC, DRC, drc_reg);
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}
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static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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static void sdram_enable(void)
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{
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int i;
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@ -470,7 +468,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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delay();
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print_debug("Ram enable 9\n");
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set_initialize_complete(ctrl);
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set_initialize_complete();
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delay();
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delay();
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@ -495,11 +493,8 @@ DIMM-independant configuration functions:
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/**
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* Set only what I need until it works, then make it figure things out on boot
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* assumes only one DIMM is populated.
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*
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* @param ctrl PCI addresses of memory controller functions, and SMBus
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* addresses of DIMM slots on the mainboard.
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*/
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static void sdram_set_registers(const struct mem_controller *ctrl)
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static void sdram_set_registers(void)
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{
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/*
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print_debug("Before configuration:\n");
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@ -507,13 +502,13 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
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*/
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}
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static void spd_set_row_attributes(const struct mem_controller *ctrl, uint8_t dimm_mask)
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static void spd_set_row_attributes(uint8_t dimm_mask)
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{
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int i;
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uint16_t row_attributes = 0;
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for (i = 0; i < DIMM_SOCKETS; i++) {
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uint16_t dimm = ctrl->channel0[i];
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u8 dimm = DIMM0 + i;
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struct dimm_size page_size;
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struct dimm_size sdram_width;
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@ -544,7 +539,7 @@ static void spd_set_row_attributes(const struct mem_controller *ctrl, uint8_t di
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pci_write_config16(NORTHBRIDGE_MMC, DRA, row_attributes);
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}
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static void spd_set_dram_controller_mode(const struct mem_controller *ctrl, uint8_t dimm_mask)
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static void spd_set_dram_controller_mode(uint8_t dimm_mask)
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{
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int i;
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@ -558,7 +553,7 @@ static void spd_set_dram_controller_mode(const struct mem_controller *ctrl, uint
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controller_mode |= (2 << 10); // FIXME: Undocumented, really needed?????
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for (i = 0; i < DIMM_SOCKETS; i++) {
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uint16_t dimm = ctrl->channel0[i];
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u8 dimm = DIMM0 + i;
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uint32_t dimm_refresh_mode;
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int value;
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u8 tRCD, tRP;
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@ -610,7 +605,7 @@ static void spd_set_dram_controller_mode(const struct mem_controller *ctrl, uint
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pci_write_config32(NORTHBRIDGE_MMC, DRC, controller_mode);
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}
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static void spd_set_dram_timing(const struct mem_controller *ctrl, uint8_t dimm_mask)
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static void spd_set_dram_timing(uint8_t dimm_mask)
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{
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int i;
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u32 dram_timing;
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@ -623,7 +618,7 @@ static void spd_set_dram_timing(const struct mem_controller *ctrl, uint8_t dimm_
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uint8_t slowest_active_to_precharge_delay = 0;
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for (i = 0; i < DIMM_SOCKETS; i++) {
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uint16_t dimm = ctrl->channel0[i];
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u8 dimm = DIMM0 + i;
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int value;
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uint32_t current_cas_latency;
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uint32_t dimm_compatible_cas_latencies;
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@ -788,14 +783,14 @@ static void spd_set_dram_timing(const struct mem_controller *ctrl, uint8_t dimm_
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pci_write_config32(NORTHBRIDGE_MMC, DRT, dram_timing);
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}
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static void spd_set_dram_size(const struct mem_controller *ctrl, uint8_t dimm_mask)
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static void spd_set_dram_size(uint8_t dimm_mask)
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{
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int i;
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int total_dram = 0;
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uint32_t drb_reg = 0;
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for (i = 0; i < DIMM_SOCKETS; i++) {
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uint16_t dimm = ctrl->channel0[i];
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u8 dimm = DIMM0 + i;
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struct dimm_size sz;
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if (!(dimm_mask & (1 << i))) {
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@ -818,7 +813,7 @@ static void spd_set_dram_size(const struct mem_controller *ctrl, uint8_t dimm_ma
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}
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static void spd_set_dram_pwr_management(const struct mem_controller *ctrl)
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static void spd_set_dram_pwr_management(void)
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{
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uint32_t pwrmg_reg;
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@ -826,7 +821,7 @@ static void spd_set_dram_pwr_management(const struct mem_controller *ctrl)
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pci_write_config32(NORTHBRIDGE_MMC, PWRMG, pwrmg_reg);
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}
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static void spd_set_dram_throttle_control(const struct mem_controller *ctrl)
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static void spd_set_dram_throttle_control(void)
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{
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uint32_t dtc_reg = 0;
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@ -874,28 +869,28 @@ static void spd_set_dram_throttle_control(const struct mem_controller *ctrl)
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pci_write_config32(NORTHBRIDGE_MMC, DTC, dtc_reg);
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}
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static void spd_update(const struct mem_controller *ctrl, u8 reg, u32 new_value)
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static void spd_update(u8 reg, u32 new_value)
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{
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#if CONFIG_DEBUG_RAM_SETUP
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u32 value1 = pci_read_config32(ctrl->d0, reg);
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u32 value1 = pci_read_config32(NORTHBRIDGE_MMC, reg);
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#endif
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pci_write_config32(ctrl->d0, reg, new_value);
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pci_write_config32(NORTHBRIDGE_MMC, reg, new_value);
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#if CONFIG_DEBUG_RAM_SETUP
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u32 value2 = pci_read_config32(ctrl->d0, reg);
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u32 value2 = pci_read_config32(NORTHBRIDGE_MMC, reg);
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PRINTK_DEBUG("update reg %02x, old: %08x, new: %08x, read back: %08x\n", reg, value1, new_value, value2);
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#endif
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}
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/* if ram still doesn't work do this function */
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static void spd_set_undocumented_registers(const struct mem_controller *ctrl)
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static void spd_set_undocumented_registers(void)
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{
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spd_update(ctrl, 0x74, 0x00000001);
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spd_update(ctrl, 0x78, 0x001fe974);
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spd_update(ctrl, 0x80, 0x00af0039);
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spd_update(ctrl, 0x84, 0x0000033c);
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spd_update(ctrl, 0x88, 0x00000010);
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spd_update(0x74, 0x00000001);
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spd_update(0x78, 0x001fe974);
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spd_update(0x80, 0x00af0039);
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spd_update(0x84, 0x0000033c);
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spd_update(0x88, 0x00000010);
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spd_update(ctrl, 0xc0, 0x00000003);
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spd_update(0xc0, 0x00000003);
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}
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static void northbridge_set_registers(void)
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@ -961,26 +956,26 @@ static void northbridge_set_registers(void)
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printk(BIOS_DEBUG, "Initial Northbridge registers have been set.\n");
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}
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static void sdram_set_spd_registers(const struct mem_controller *ctrl)
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static void sdram_set_spd_registers(void)
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{
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uint8_t dimm_mask;
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PRINTK_DEBUG("Reading SPD data...\n");
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dimm_mask = spd_get_supported_dimms(ctrl);
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dimm_mask = spd_get_supported_dimms();
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if (dimm_mask == 0) {
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print_debug("No usable memory for this controller\n");
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} else {
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PRINTK_DEBUG("DIMM MASK: %02x\n", dimm_mask);
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spd_set_row_attributes(ctrl, dimm_mask);
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spd_set_dram_controller_mode(ctrl, dimm_mask);
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spd_set_dram_timing(ctrl, dimm_mask);
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spd_set_dram_size(ctrl, dimm_mask);
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spd_set_dram_pwr_management(ctrl);
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spd_set_dram_throttle_control(ctrl);
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spd_set_undocumented_registers(ctrl);
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spd_set_row_attributes(dimm_mask);
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spd_set_dram_controller_mode(dimm_mask);
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spd_set_dram_timing(dimm_mask);
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spd_set_dram_size(dimm_mask);
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spd_set_dram_pwr_management();
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spd_set_dram_throttle_control();
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spd_set_undocumented_registers();
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}
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/* Setup Initial Northbridge Registers */
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@ -21,18 +21,13 @@
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#ifndef NORTHBRIDGE_INTEL_I855_RAMINIT_H
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#define NORTHBRIDGE_INTEL_I855_RAMINIT_H
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/* i855 Northbridge PCI device */
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/* i855 Northbridge PCI devices */
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#define NORTHBRIDGE PCI_DEV(0, 0, 0)
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#define NORTHBRIDGE_MMC PCI_DEV(0, 0, 1)
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/* The i855 supports max. 2 dual-sided SO-DIMMs. */
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#define DIMM_SOCKETS 2
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struct mem_controller {
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device_t d0;
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uint16_t channel0[DIMM_SOCKETS];
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};
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void sdram_initialize(int controllers, const struct mem_controller *ctrl);
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void sdram_initialize(void);
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#endif /* NORTHBRIDGE_INTEL_I855_RAMINIT_H */
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