libpayload: Add more libpci-compatibility (#defines)
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6417 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -42,6 +42,8 @@ typedef u32 pcidev_t;
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#define REG_SUBSYS_VENDOR_ID 0x2C
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#define REG_SUBSYS_ID 0x2E
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#define REG_COMMAND_IO (1 << 0)
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#define REG_COMMAND_MEM (1 << 1)
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#define REG_COMMAND_BM (1 << 2)
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#define HEADER_TYPE_NORMAL 0
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@ -39,6 +39,32 @@
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#define PCI_SUBSYSTEM_VENDOR_ID REG_SUBSYS_VENDOR_ID
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#define PCI_SUBSYSTEM_ID REG_SUBSYS_ID
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#define PCI_COMMAND REG_COMMAND
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#define PCI_COMMAND_IO REG_COMMAND_IO
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#define PCI_COMMAND_MEMORY REG_COMMAND_MEM
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#define PCI_COMMAND_MASTER REG_COMMAND_BM
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#define PCI_HEADER_TYPE REG_HEADER_TYPE
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#define PCI_HEADER_TYPE_NORMAL HEADER_TYPE_NORMAL
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#define PCI_HEADER_TYPE_BRIDGE HEADER_TYPE_BRIDGE
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#define PCI_HEADER_TYPE_CARDBUS HEADER_TYPE_CARDBUS
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#define PCI_BASE_ADDRESS_0 0x10
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#define PCI_BASE_ADDRESS_1 0x14
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#define PCI_BASE_ADDRESS_2 0x18
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#define PCI_BASE_ADDRESS_3 0x1c
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#define PCI_BASE_ADDRESS_4 0x20
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#define PCI_BASE_ADDRESS_5 0x24
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#define PCI_BASE_ADDRESS_SPACE 1 // mask
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#define PCI_BASE_ADDRESS_SPACE_IO 1
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#define PCI_BASE_ADDRESS_SPACE_MEM 0
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#define PCI_BASE_ADDRESS_IO_MASK ~0xf
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#define PCI_BASE_ADDRESS_MEM_MASK ~0x3
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#define PCI_ROM_ADDRESS 0x30
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#define PCI_ROM_ADDRESS1 0x38 // on bridges
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#define PCI_ROM_ADDRESS_MASK ~0x7ff
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struct pci_dev {
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u16 domain;
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u8 bus, dev, func;
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