X60: enable Cx power saving modes

Change-Id: Ib03d9aa77050edde2538b80b32158cb3f0610be6
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/331
Tested-by: build bot (Jenkins)
This commit is contained in:
Sven Schnelle 2011-10-23 16:57:50 +02:00
parent f02c396f26
commit 6eb8bef25e
3 changed files with 32 additions and 0 deletions

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@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SUPERIO_NSC_PC87392 select SUPERIO_NSC_PC87392
select EC_LENOVO_PMH7 select EC_LENOVO_PMH7
select EC_LENOVO_H8 select EC_LENOVO_H8
select DRIVERS_ICS_954309
select BOARD_HAS_FADT select BOARD_HAS_FADT
select HAVE_OPTION_TABLE select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE select HAVE_PIRQ_TABLE

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@ -60,6 +60,8 @@ chip northbridge/intel/i945
register "gpe0_en" = "0x11000006" register "gpe0_en" = "0x11000006"
register "alt_gp_smi_en" = "0x1000" register "alt_gp_smi_en" = "0x1000"
register "c4onc3_enable" = "1"
device pci 1b.0 on # Audio Cnotroller device pci 1b.0 on # Audio Cnotroller
subsystemid 0x17aa 0x2010 subsystemid 0x17aa 0x2010
end end
@ -174,6 +176,22 @@ chip northbridge/intel/i945
end end
device pci 1f.3 on # SMBUS device pci 1f.3 on # SMBUS
subsystemid 0x17aa 0x200f subsystemid 0x17aa 0x200f
chip drivers/ics/954309
register "reg0" = "0x2e"
register "reg1" = "0xf7"
register "reg2" = "0x3c"
register "reg3" = "0x20"
register "reg4" = "0x01"
register "reg5" = "0x00"
register "reg6" = "0x1b"
register "reg7" = "0x01"
register "reg8" = "0x54"
register "reg9" = "0xff"
register "reg10" = "0xff"
register "reg11" = "0x07"
device i2c 69 on end
end
end end
end end
chip southbridge/ricoh/rl5c476 chip southbridge/ricoh/rl5c476

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@ -36,6 +36,19 @@
#include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/i945.h>
#include <pc80/mc146818rtc.h> #include <pc80/mc146818rtc.h>
#include "dock.h" #include "dock.h"
#include <arch/x86/include/arch/acpigen.h>
static struct cst_entry cst_entries[] = {
{ 0x7f, 1, 2, 0, 1, 1, 1, 1000 },
{ 0x01, 8, 0, 0, DEFAULT_PMBASE + LV2, 2, 1, 500 },
{ 0x01, 8, 0, 0, DEFAULT_PMBASE + LV3, 2, 17, 250 },
};
int get_cst_entries(struct cst_entry **entries)
{
*entries = cst_entries;
return ARRAY_SIZE(cst_entries);
}
static void mainboard_enable(device_t dev) static void mainboard_enable(device_t dev)
{ {