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mainboard: Fix comment about early GPIOs 

These boards program the early GPIO table in bootblock, not romstage.

Change-Id: Iae9353d106483f30cefa2d035d96e63e4c127261
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Sean Rhodes <admin@starlabs.systems>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit is contained in:
Angel Pons 2021-12-18 13:16:06 +01:00
parent 52ad866939
commit 6ebb3b60a4
16 changed files with 16 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/asrock/h110m/include/gpio.h
View File

@ -455,7 +455,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_I10, DN_20K, PLTRST, NF1),
};
/* Early pad configuration in romstage */
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
/* ------- GPIO Group GPP_A ------- */
/* GPP_A0 - RCIN# */

2
src/mainboard/google/glados/variants/asuka/include/variant/gpio.h
View File

@ -214,7 +214,7 @@ static const struct pad_config gpio_table[] = {
/* LANPHYC */ PAD_NC(GPD11, NONE),
};
/* Early pad configuration in romstage. */
/* Early pad configuration in bootblock. */
static const struct pad_config early_gpio_table[] = {
/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP),
/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),

2
src/mainboard/google/glados/variants/caroline/include/variant/gpio.h
View File

@ -231,7 +231,7 @@ static const struct pad_config gpio_table[] = {
/* LANPHYC */ PAD_NC(GPD11, NONE),
};
/* Early pad configuration in romstage. */
/* Early pad configuration in bootblock. */
static const struct pad_config early_gpio_table[] = {
/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */
/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),

2
src/mainboard/google/glados/variants/cave/include/variant/gpio.h
View File

@ -223,7 +223,7 @@ static const struct pad_config gpio_table[] = {
/* LANPHYC */ PAD_NC(GPD11, NONE),
};
/* Early pad configuration in romstage. */
/* Early pad configuration in bootblock. */
static const struct pad_config early_gpio_table[] = {
/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */
/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),

2
src/mainboard/google/glados/variants/chell/include/variant/gpio.h
View File

@ -217,7 +217,7 @@ static const struct pad_config gpio_table[] = {
/* LANPHYC */ PAD_NC(GPD11, NONE),
};
/* Early pad configuration in romstage. */
/* Early pad configuration in bootblock. */
static const struct pad_config early_gpio_table[] = {
/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */
/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */

2
src/mainboard/google/glados/variants/glados/include/variant/gpio.h
View File

@ -220,7 +220,7 @@ static const struct pad_config gpio_table[] = {
/* LANPHYC */ /* GPD11 */
};
/* Early pad configuration in romstage. */
/* Early pad configuration in bootblock. */
static const struct pad_config early_gpio_table[] = {
/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */
/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */

2
src/mainboard/google/glados/variants/lars/include/variant/gpio.h
View File

@ -208,7 +208,7 @@ static const struct pad_config gpio_table[] = {
/* LANPHYC */ PAD_NC(GPD11, NONE),
};
/* Early pad configuration in romstage. */
/* Early pad configuration in bootblock. */
static const struct pad_config early_gpio_table[] = {
/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */
/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */

2
src/mainboard/google/glados/variants/sentry/include/variant/gpio.h
View File

@ -216,7 +216,7 @@ static const struct pad_config gpio_table[] = {
/* LANPHYC */ PAD_NC(GPD11, NONE),
};
/* Early pad configuration in romstage. */
/* Early pad configuration in bootblock. */
static const struct pad_config early_gpio_table[] = {
/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */
/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP),

2
src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h
View File

@ -257,7 +257,7 @@ static const struct pad_config gpio_table[] = {
/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
};
/* Early pad configuration in romstage. */
/* Early pad configuration in bootblock. */
static const struct pad_config early_gpio_table[] = {
/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),

2
src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h
View File

@ -193,7 +193,7 @@ static const struct pad_config gpio_table[] = {
/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
};
/* Early pad configuration in romstage. */
/* Early pad configuration in bootblock. */
static const struct pad_config early_gpio_table[] = {
/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),

2
src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h
View File

@ -193,7 +193,7 @@ static const struct pad_config gpio_table[] = {
/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
};
/* Early pad configuration in romstage. */
/* Early pad configuration in bootblock. */
static const struct pad_config early_gpio_table[] = {
/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),

2
src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h
View File

@ -159,7 +159,7 @@ static const struct pad_config gpio_table[] = {
};
/* Early pad configuration in romstage. */
/* Early pad configuration in bootblock. */
static const struct pad_config early_gpio_table[] = {
/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),

2
src/mainboard/intel/kunimitsu/gpio.h
View File

@ -217,7 +217,7 @@ static const struct pad_config gpio_table[] = {
/* LANPHYC */ PAD_NC(GPD11, NONE),
};
/* Early pad configuration in romstage. */
/* Early pad configuration in bootblock. */
static const struct pad_config early_gpio_table[] = {
/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */
/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP),

2
src/mainboard/intel/saddlebrook/gpio.h
View File

@ -245,7 +245,7 @@ static const struct pad_config gpio_table[] = {
/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
};
/* Early pad configuration in romstage. */
/* Early pad configuration in bootblock. */
static const struct pad_config early_gpio_table[] = {
/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_KEPLER */
};

2
src/mainboard/starlabs/labtop/variants/tgl/gpio.c
View File

@ -7,7 +7,7 @@
* using the stock BIOS and with coreboot.
*/
/* Early pad configuration in romstage. */
/* Early pad configuration in bootblock. */
const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),

2
src/mainboard/system76/lemp9/gpio.h
View File

@ -10,7 +10,7 @@
/* Name format: <pad name> / <net/pin name in schematics> */
/* Early pad configuration in romstage. */
/* Early pad configuration in bootblock. */
static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2_RXD */
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2_TXD */