GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

northbridge/intel/haswell/acpi: Use Printf() for debug prints 

Change-Id: I3f500ec46a9046a4e8ca50a85965b8e1225f8a33
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
This commit is contained in:
Felix Singer 2021-12-29 13:09:09 +01:00
parent ffe40a7a70
commit 6ed79cbddc
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/northbridge/intel/haswell/acpi/ctdp.asl
View File

@ -99,7 +99,7 @@ Scope (\_SB.PCI0.MCHC)
Return (0) Return (0)
} }
Debug = "Set TDP Down" Printf ("Set TDP Down")
/* Set CTC */ /* Set CTC */
CTCS = CTCD CTCS = CTCD
@ -135,7 +135,7 @@ Scope (\_SB.PCI0.MCHC)
Return (0) Return (0)
} }
Debug = "Set TDP Nominal" Printf ("Set TDP Nominal")
/* Set PL1 */ /* Set PL1 */
PL1V = CTDN PL1V = CTDN
@ -173,7 +173,7 @@ Scope (\_SB.PCI0.MCHC)
Return (0) Return (0)
} }
Debug = "Enable PL1 Limit" Printf ("Enable PL1 Limit")
/* Set _PPC to LFM */ /* Set _PPC to LFM */
Local0 = PSSS (LFM_) Local0 = PSSS (LFM_)
@ -201,7 +201,7 @@ Scope (\_SB.PCI0.MCHC)
Return (0) Return (0)
} }
Debug = "Disable PL1 Limit" Printf ("Disable PL1 Limit")
/* Clear PL1 CLAMP bit */ /* Clear PL1 CLAMP bit */
PL1C = 0 PL1C = 0